90 lines
1.6 KiB
Systemverilog
90 lines
1.6 KiB
Systemverilog
interface axi4lite_intf #(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 32
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);
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logic ACLK;
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logic ARESETn;
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logic AWREADY;
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logic AWVALID;
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logic [ADDR_WIDTH-1:0] AWADDR;
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logic [2:0] AWPROT;
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logic WREADY;
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logic WVALID;
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logic [DATA_WIDTH-1:0] WDATA;
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logic [DATA_WIDTH/8-1:0] WSTRB;
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logic BREADY;
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logic BVALID;
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logic [1:0] BRESP;
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logic ARREADY;
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logic ARVALID;
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logic [ADDR_WIDTH-1:0] ARADDR;
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logic [2:0] ARPROT;
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logic RREADY;
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logic RVALID;
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logic [DATA_WIDTH-1:0] RDATA;
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logic [1:0] RRESP;
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modport master (
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input ACLK,
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input ARESETn,
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input AWREADY,
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output AWVALID,
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output AWADDR,
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output AWPROT,
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input WREADY,
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output WVALID,
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output WDATA,
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output WSTRB,
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output BREADY,
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input BVALID,
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input BRESP,
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input ARREADY,
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output ARVALID,
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output ARADDR,
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output ARPROT,
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output RREADY,
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input RVALID,
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input RDATA,
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input RRESP
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);
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modport slave (
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input ACLK,
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input ARESETn,
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output AWREADY,
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input AWVALID,
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input AWADDR,
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input AWPROT,
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output WREADY,
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input WVALID,
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input WDATA,
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input WSTRB,
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input BREADY,
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output BVALID,
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output BRESP,
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output ARREADY,
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input ARVALID,
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input ARADDR,
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input ARPROT,
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input RREADY,
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output RVALID,
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output RDATA,
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output RRESP
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);
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endinterface
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