51 lines
1.2 KiB
Systemverilog
51 lines
1.2 KiB
Systemverilog
{% extends "lib/tb_base.sv" %}
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{% block seq %}
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{% sv_line_anchor %}
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##1;
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cb.rst <= '0;
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##1;
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// Write all regs in parallel burst
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for(int i=0; i<64; i++) begin
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fork
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automatic int i_fk = i;
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begin
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cpuif.write(i_fk*4, i_fk + 32'h12340000);
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end
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join_none
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end
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wait fork;
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// Verify HW value
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@cb;
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for(int i=0; i<64; i++) begin
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assert(cb.hwif_out.x[i].x.value == i + 32'h12340000)
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else $error("hwif_out.x[i] == 0x%0x. Expected 0x%0x", cb.hwif_out.x[i].x.value, i + 32'h12340000);
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end
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// Read all regs in parallel burst
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for(int i=0; i<64; i++) begin
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fork
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automatic int i_fk = i;
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begin
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cpuif.assert_read(i_fk*4, i_fk + 32'h12340000);
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end
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join_none
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end
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wait fork;
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// Mix read/writes
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for(int i=0; i<8; i++) begin
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fork
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automatic int i_fk = i;
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begin
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cpuif.write(i_fk*4, i_fk + 32'h56780000);
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cpuif.assert_read(i_fk*4, i_fk + 32'h56780000);
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end
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join_none
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end
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wait fork;
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{% endblock %}
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