67 lines
1.2 KiB
Plaintext
67 lines
1.2 KiB
Plaintext
addrmap top {
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default regwidth = 8;
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reg {
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field {
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sw=rw; hw=na;
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} r3_swwe[0:0] = 1;
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field {
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sw=rw; hw=na;
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} r4_swwel[1:1] = 0;
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} lock;
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//---------------------------------
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// via inferred signal
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//---------------------------------
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reg {
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field {
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sw=rw; hw=na;
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swwe;
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} f[8] = 0x11;
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} r1;
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reg {
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field {
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sw=rw; hw=na;
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swwel;
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} f[8] = 0x22;
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} r2;
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//---------------------------------
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// via lock register
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//---------------------------------
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reg {
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field {
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sw=rw; hw=na;
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} f[8] = 0x33;
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} r3;
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r3.f->swwe = lock.r3_swwe;
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reg {
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field {
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sw=rw; hw=na;
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} f[8] = 0x44;
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} r4;
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r4.f->swwel = lock.r4_swwel;
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//---------------------------------
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// via prop ref chaining
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//---------------------------------
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reg {
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field {
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sw=rw; hw=na;
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} f[8] = 0x55;
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} r5;
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r5.f->swwe = r3.f->swwe;
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reg {
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field {
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sw=rw; hw=na;
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} f[8] = 0x66;
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} r6;
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r6.f->swwe = r4.f->swwel; // intentionally opposite!
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};
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