92 lines
3.0 KiB
ReStructuredText
92 lines
3.0 KiB
ReStructuredText
Introduction
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============
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PeakRDL-BusDecoder is a free and open-source bus decoder generator for hierarchical
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SystemRDL address maps. It produces a synthesizable SystemVerilog RTL module that
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accepts a single CPU interface (slave side) and fans transactions out to multiple
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child address spaces (master side).
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This tool **does not** generate register storage or field logic. It is strictly a
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bus-routing layer that decodes addresses and forwards requests to child blocks.
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This is particularly useful for:
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* Creating hierarchical register maps with multiple sub-components
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* Splitting a single CPU interface bus to serve multiple independent register blocks
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* Organizing large address spaces into logical sub-regions
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* Implementing address decode logic for multi-drop bus architectures
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The generated bus decoder provides:
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* Fully synthesizable SystemVerilog RTL (IEEE 1800-2012)
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* A top-level slave CPU interface and per-child master CPU interfaces
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* Address decode logic that routes transactions to child address maps
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* Support for APB3, APB4, and AXI4-Lite (plus plugin-defined CPU interfaces)
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* Configurable decode depth and array unrolling
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Quick Start
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-----------
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The easiest way to use PeakRDL-BusDecoder is via the
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`PeakRDL command line tool <https://peakrdl.readthedocs.io/>`_:
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.. code-block:: bash
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# Install PeakRDL-BusDecoder along with the command-line tool
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python3 -m pip install peakrdl-busdecoder[cli]
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# Export!
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peakrdl busdecoder atxmega_spi.rdl -o busdecoder/ --cpuif axi4-lite
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The exporter writes two files:
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* A SystemVerilog module (the bus decoder)
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* A SystemVerilog package (constants like data width and per-child address widths)
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Key command-line options:
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* ``--cpuif``: Select the CPU interface (``apb3``, ``apb3-flat``, ``apb4``, ``apb4-flat``, ``axi4-lite``, ``axi4-lite-flat``)
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* ``--module-name``: Override the generated module name
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* ``--package-name``: Override the generated package name
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* ``--addr-width``: Override the slave address width
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* ``--unroll``: Unroll arrayed children into discrete interfaces
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* ``--max-decode-depth``: Control how far the decoder descends into hierarchy
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Looking for VHDL?
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-----------------
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This project generates SystemVerilog RTL. If you prefer using VHDL, check out
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the sister project which aims to be a feature-equivalent fork of
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PeakRDL-BusDecoder: `PeakRDL-busdecoder-VHDL <https://peakrdl-busdecoder-vhdl.readthedocs.io>`_
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Links
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-----
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- `Source repository <https://github.com/arnavsacheti/PeakRDL-BusDecoder>`_
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- `Release Notes <https://github.com/arnavsacheti/PeakRDL-BusDecoder/releases>`_
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- `Issue tracker <https://github.com/arnavsacheti/PeakRDL-BusDecoder/issues>`_
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- `PyPi <https://pypi.org/project/peakrdl-busdecoder>`_
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- `SystemRDL Specification <http://accellera.org/downloads/standards/systemrdl>`_
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.. toctree::
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:hidden:
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self
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architecture
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configuring
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limitations
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licensing
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api
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.. toctree::
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:hidden:
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:caption: CPU Interfaces
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cpuif/introduction
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cpuif/apb
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cpuif/axi4lite
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cpuif/internal_protocol
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cpuif/customizing
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