1e09da6dbf
Fix APB PREADY signal to assert during error conditions Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
105 lines
4.3 KiB
Python
105 lines
4.3 KiB
Python
from collections import deque
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from typing import TYPE_CHECKING, overload
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from systemrdl.node import AddressableNode
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from ...sv_int import SVInt
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from ...utils import clog2, get_indexed_path
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from ..base_cpuif import BaseCpuif
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from .axi4_lite_interface import AXI4LiteFlatInterface
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if TYPE_CHECKING:
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from ...exporter import BusDecoderExporter
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class AXI4LiteCpuifFlat(BaseCpuif):
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"""Verilator-friendly variant that flattens the AXI4-Lite interface ports."""
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template_path = "axi4_lite_tmpl.sv"
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def __init__(self, exp: "BusDecoderExporter") -> None:
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super().__init__(exp)
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self._interface = AXI4LiteFlatInterface(self)
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@property
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def is_interface(self) -> bool:
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return self._interface.is_interface
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@property
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def port_declaration(self) -> str:
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"""Returns the port declaration for the AXI4-Lite interface."""
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return self._interface.get_port_declaration("s_axil_", "m_axil_")
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@overload
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def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
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@overload
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def signal(self, signal: str, node: AddressableNode, indexer: str | None = None) -> str: ...
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def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
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return self._interface.signal(signal, node, indexer)
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def fanout(self, node: AddressableNode, array_stack: deque[int]) -> str:
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fanout: dict[str, str] = {}
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waddr_comp = [f"{self.signal('AWADDR')}"]
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raddr_comp = [f"{self.signal('ARADDR')}"]
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for i, stride in enumerate(array_stack):
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offset = f"(gi{i}*{SVInt(stride, self.addr_width)})"
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waddr_comp.append(offset)
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raddr_comp.append(offset)
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wr_sel = f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
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rd_sel = f"cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
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# Write address channel
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fanout[self.signal("AWVALID", node, "gi")] = wr_sel
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fanout[self.signal("AWADDR", node, "gi")] = f"{{{'-'.join(waddr_comp)}}}[{clog2(node.size) - 1}:0]"
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fanout[self.signal("AWPROT", node, "gi")] = self.signal("AWPROT")
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# Write data channel
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fanout[self.signal("WVALID", node, "gi")] = wr_sel
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fanout[self.signal("WDATA", node, "gi")] = "cpuif_wr_data"
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fanout[self.signal("WSTRB", node, "gi")] = "cpuif_wr_byte_en"
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# Write response channel (master -> slave)
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fanout[self.signal("BREADY", node, "gi")] = self.signal("BREADY")
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# Read address channel
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fanout[self.signal("ARVALID", node, "gi")] = rd_sel
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fanout[self.signal("ARADDR", node, "gi")] = f"{{{'-'.join(raddr_comp)}}}[{clog2(node.size) - 1}:0]"
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fanout[self.signal("ARPROT", node, "gi")] = self.signal("ARPROT")
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# Read data channel (master -> slave)
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fanout[self.signal("RREADY", node, "gi")] = self.signal("RREADY")
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return "\n".join(f"assign {lhs} = {rhs};" for lhs, rhs in fanout.items())
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def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
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fanin: dict[str, str] = {}
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if node is None:
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fanin["cpuif_wr_ack"] = "'0"
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fanin["cpuif_wr_err"] = "'0"
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if error:
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fanin["cpuif_wr_ack"] = "'1"
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fanin["cpuif_wr_err"] = "cpuif_wr_sel.cpuif_err"
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else:
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# Read side: ack comes from RVALID; err if RRESP[1] is set (SLVERR/DECERR)
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fanin["cpuif_wr_ack"] = self.signal("BVALID", node, "i")
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fanin["cpuif_wr_err"] = f"{self.signal('BRESP', node, 'i')}[1]"
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return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
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def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
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fanin: dict[str, str] = {}
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if node is None:
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fanin["cpuif_rd_ack"] = "'0"
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fanin["cpuif_rd_err"] = "'0"
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fanin["cpuif_rd_data"] = "'0"
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if error:
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fanin["cpuif_rd_ack"] = "'1"
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fanin["cpuif_rd_err"] = "cpuif_rd_sel.cpuif_err"
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else:
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fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
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fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
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fanin["cpuif_rd_data"] = self.signal("RDATA", node, "i")
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return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
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