c63b2cbab2
* Downsize paddr bits * Updated Test suite to use offset aligned address * fix for apb3 and axi4lite * modified structure to pass hierarchy information --------- Co-authored-by: Byron Lathi <bslathi19@gmail.com>
62 lines
1.8 KiB
Python
62 lines
1.8 KiB
Python
from collections import deque
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from typing import TYPE_CHECKING
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from systemrdl.node import AddressableNode
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from systemrdl.walker import WalkerAction
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from ..body import Body, ForLoopBody
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from ..design_state import DesignState
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from ..listener import BusDecoderListener
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if TYPE_CHECKING:
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from .base_cpuif import BaseCpuif
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class FanoutGenerator(BusDecoderListener):
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def __init__(self, ds: DesignState, cpuif: "BaseCpuif") -> None:
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super().__init__(ds)
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self._cpuif = cpuif
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self._stack: deque[Body] = deque()
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self._stack.append(Body())
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def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
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action = super().enter_AddressableComponent(node)
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should_generate = action == WalkerAction.SkipDescendants
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if not should_generate and self._ds.max_decode_depth == 0:
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for child in node.children():
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if isinstance(child, AddressableNode):
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break
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else:
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should_generate = True
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if not should_generate:
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return action
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if node.array_dimensions:
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for i, dim in enumerate(node.array_dimensions):
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fb = ForLoopBody(
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"genvar",
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f"gi{i}",
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dim,
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)
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self._stack.append(fb)
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self._stack[-1] += self._cpuif.fanout(node, self._array_stride_stack)
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return action
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def exit_AddressableComponent(self, node: AddressableNode) -> None:
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if node.array_dimensions:
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for _ in node.array_dimensions:
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b = self._stack.pop()
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if not b:
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continue
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self._stack[-1] += b
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super().exit_AddressableComponent(node)
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def __str__(self) -> str:
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return "\n".join(map(str, self._stack))
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