143 lines
5.1 KiB
Python
143 lines
5.1 KiB
Python
import os
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from importlib.metadata import version
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from pathlib import Path
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from typing import TYPE_CHECKING, Any, TypedDict
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import jinja2 as jj
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from systemrdl.node import AddrmapNode, RootNode
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from systemrdl.walker import RDLSteerableWalker
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from typing_extensions import Unpack
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from .cpuif import BaseCpuif
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from .cpuif.apb4 import APB4Cpuif
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from .decode_logic_gen import DecodeLogicFlavor, DecodeLogicGenerator
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from .design_state import DesignState
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from .identifier_filter import kw_filter as kwf
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from .listener import BusDecoderListener
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from .struct_gen import StructGenerator
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from .sv_int import SVInt
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from .utils import clog2
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from .validate_design import DesignValidator
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class ExporterKwargs(TypedDict, total=False):
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cpuif_cls: type[BaseCpuif]
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module_name: str
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package_name: str
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address_width: int
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cpuif_unroll: bool
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reuse_hwif_typedefs: bool
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max_decode_depth: int
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if TYPE_CHECKING:
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pass
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class BusDecoderExporter:
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cpuif: BaseCpuif
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ds: DesignState
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def __init__(self, **kwargs: Unpack[ExporterKwargs]) -> None:
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# Check for stray kwargs
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if kwargs:
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raise TypeError(f"got an unexpected keyword argument '{next(iter(kwargs.keys()))}'")
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fs_loader = jj.FileSystemLoader(Path(__file__).parent)
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c_loader = jj.ChoiceLoader(
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[
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fs_loader,
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jj.PrefixLoader(
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{"base": fs_loader},
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delimiter=":",
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),
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]
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)
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self.jj_env = jj.Environment(
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loader=c_loader,
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undefined=jj.StrictUndefined,
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)
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self.jj_env.filters["kwf"] = kwf
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self.jj_env.filters["walk"] = self.walk
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self.jj_env.filters["clog2"] = clog2
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def export(self, node: RootNode | AddrmapNode, output_dir: str, **kwargs: Unpack[ExporterKwargs]) -> None:
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"""
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Parameters
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----------
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node: AddrmapNode
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Top-level SystemRDL node to export.
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output_dir: str
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Path to the output directory where generated SystemVerilog will be written.
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Output includes two files: a module definition and package definition.
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cpuif_cls: :class:`peakrdl_busdecoder.cpuif.CpuifBase`
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Specify the class type that implements the CPU interface of your choice.
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Defaults to AMBA APB4.
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module_name: str
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Override the SystemVerilog module name. By default, the module name
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is the top-level node's name.
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package_name: str
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Override the SystemVerilog package name. By default, the package name
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is the top-level node's name with a "_pkg" suffix.
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address_width: int
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Override the CPU interface's address width. By default, address width
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is sized to the contents of the busdecoder.
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cpuif_unroll: bool
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Unroll arrayed addressable nodes into separate instances in the CPU
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interface. By default, arrayed nodes are kept as arrays.
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max_decode_depth: int
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Maximum depth for address decoder to descend into nested addressable
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components. A value of 0 decodes all levels (infinite depth). A value
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of 1 decodes only top-level children. A value of 2 decodes top-level
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and one level deeper, etc. By default, the decoder descends 1 level deep.
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"""
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# If it is the root node, skip to top addrmap
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if isinstance(node, RootNode):
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top_node = node.top
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else:
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top_node = node
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self.ds = DesignState(top_node, kwargs) # ty: ignore
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cpuif_cls: type[BaseCpuif] = kwargs.pop("cpuif_cls", None) or APB4Cpuif
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# Check for stray kwargs
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if kwargs:
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raise TypeError(f"got an unexpected keyword argument '{next(iter(kwargs.keys()))}'")
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# Construct exporter components
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self.cpuif = cpuif_cls(self)
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# Validate that there are no unsupported constructs
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DesignValidator(self).do_validate()
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# Build Jinja template context
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context = {
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"version": version("peakrdl-busdecoder"),
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"cpuif": self.cpuif,
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"cpuif_decode": DecodeLogicGenerator,
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"cpuif_select": StructGenerator,
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"cpuif_decode_flavor": DecodeLogicFlavor,
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"ds": self.ds,
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"SVInt": SVInt,
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}
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# Write out design
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os.makedirs(output_dir, exist_ok=True)
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package_file_path = os.path.join(output_dir, self.ds.package_name + ".sv")
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template = self.jj_env.get_template("package_tmpl.sv")
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stream = template.stream(context)
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stream.dump(package_file_path)
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module_file_path = os.path.join(output_dir, self.ds.module_name + ".sv")
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template = self.jj_env.get_template("module_tmpl.sv")
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stream = template.stream(context)
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stream.dump(module_file_path)
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def walk(self, listener_cls: type[BusDecoderListener], **kwargs: dict[str, Any]) -> str:
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walker = RDLSteerableWalker()
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listener = listener_cls(self.ds, **kwargs)
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walker.walk(self.ds.top_node, listener, skip_top=True)
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return str(listener)
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