311 lines
11 KiB
Python
311 lines
11 KiB
Python
"""APB3 smoke tests generated from SystemRDL sources."""
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from __future__ import annotations
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from typing import Any
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import cocotb
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from cocotb.triggers import RisingEdge, Timer
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from tests.cocotb_lib.handle_utils import SignalHandle
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from tests.cocotb_lib.protocol_utils import (
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all_index_pairs,
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find_invalid_address,
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get_int,
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load_config,
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set_value,
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start_clock,
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)
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class _Apb3SlaveShim:
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"""Accessor for the APB3 slave signals on the DUT."""
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def __init__(self, dut):
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prefix = "s_apb"
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self.PCLK = getattr(dut, f"{prefix}_PCLK", None)
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self.PRESETn = getattr(dut, f"{prefix}_PRESETn", None)
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self.PSEL = getattr(dut, f"{prefix}_PSEL")
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self.PENABLE = getattr(dut, f"{prefix}_PENABLE")
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self.PWRITE = getattr(dut, f"{prefix}_PWRITE")
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self.PADDR = getattr(dut, f"{prefix}_PADDR")
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self.PWDATA = getattr(dut, f"{prefix}_PWDATA")
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self.PRDATA = getattr(dut, f"{prefix}_PRDATA")
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self.PREADY = getattr(dut, f"{prefix}_PREADY")
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self.PSLVERR = getattr(dut, f"{prefix}_PSLVERR")
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def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dict[str, Any]]:
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table: dict[str, dict[str, Any]] = {}
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for master in masters_cfg:
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prefix = master["port_prefix"]
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entry = {
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"indices": [tuple(idx) for idx in master["indices"]] or [tuple()],
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"outputs": {
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"PSEL": SignalHandle(dut, f"{prefix}_PSEL"),
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"PENABLE": SignalHandle(dut, f"{prefix}_PENABLE"),
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"PWRITE": SignalHandle(dut, f"{prefix}_PWRITE"),
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"PADDR": SignalHandle(dut, f"{prefix}_PADDR"),
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"PWDATA": SignalHandle(dut, f"{prefix}_PWDATA"),
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},
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"inputs": {
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"PRDATA": SignalHandle(dut, f"{prefix}_PRDATA"),
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"PREADY": SignalHandle(dut, f"{prefix}_PREADY"),
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"PSLVERR": SignalHandle(dut, f"{prefix}_PSLVERR"),
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},
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"inst_size": master["inst_size"],
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"inst_address": master["inst_address"],
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}
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table[master["inst_name"]] = entry
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return table
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def _write_pattern(address: int, width: int) -> int:
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mask = (1 << width) - 1
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return ((address * 0x2041) ^ 0xCAFEBABE) & mask
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def _read_pattern(address: int, width: int) -> int:
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mask = (1 << width) - 1
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return ((address ^ 0x0BAD_F00D) + width) & mask
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@cocotb.test()
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async def test_apb3_address_decoding(dut) -> None:
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"""Exercise the APB3 slave interface against sampled register addresses."""
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config = load_config()
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slave = _Apb3SlaveShim(dut)
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masters = _build_master_table(dut, config["masters"])
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await start_clock(slave.PCLK)
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if slave.PRESETn is not None:
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slave.PRESETn.value = 1
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slave.PSEL.value = 0
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slave.PENABLE.value = 0
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slave.PWRITE.value = 0
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slave.PADDR.value = 0
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slave.PWDATA.value = 0
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for master_name, idx in all_index_pairs(masters):
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entry = masters[master_name]
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set_value(entry["inputs"]["PRDATA"], idx, 0)
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set_value(entry["inputs"]["PREADY"], idx, 0)
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set_value(entry["inputs"]["PSLVERR"], idx, 0)
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if slave.PCLK is not None:
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await RisingEdge(slave.PCLK)
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else:
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await Timer(1, unit="ns")
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addr_mask = (1 << config["address_width"]) - 1
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for txn in config["transactions"]:
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master_name = txn["master"]
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index = tuple(txn["index"])
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entry = masters[master_name]
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address = txn["address"] & addr_mask
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write_data = _write_pattern(address, config["data_width"])
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set_value(entry["inputs"]["PREADY"], index, 0)
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set_value(entry["inputs"]["PSLVERR"], index, 0)
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# ------------------------------------------------------------------
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# Setup phase
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# ------------------------------------------------------------------
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slave.PADDR.value = address
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slave.PWDATA.value = write_data
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slave.PWRITE.value = 1
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slave.PSEL.value = 1
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slave.PENABLE.value = 0
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dut._log.info(
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f"Starting transaction {txn['label']} to {master_name}{index} at address 0x{address:08X}"
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)
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master_address = (address - entry["inst_address"]) % entry["inst_size"]
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if slave.PCLK is not None:
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await RisingEdge(slave.PCLK)
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else:
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await Timer(1, unit="ns")
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assert get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} should assert PSEL for write"
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assert get_int(entry["outputs"]["PENABLE"], index) == 0, (
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f"{master_name} must hold PENABLE low in setup"
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)
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assert get_int(entry["outputs"]["PWRITE"], index) == 1, f"{master_name} should see write direction"
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assert get_int(entry["outputs"]["PADDR"], index) == master_address, (
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f"{master_name} must receive write address"
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)
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assert get_int(entry["outputs"]["PWDATA"], index) == write_data, (
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f"{master_name} must receive write data"
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)
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for other_name, other_idx in all_index_pairs(masters):
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if other_name == master_name and other_idx == index:
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continue
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other_entry = masters[other_name]
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assert get_int(other_entry["outputs"]["PSEL"], other_idx) == 0, (
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f"{other_name}{other_idx} should remain idle during {txn['label']}"
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)
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# ------------------------------------------------------------------
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# Access phase
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# ------------------------------------------------------------------
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set_value(entry["inputs"]["PREADY"], index, 1)
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slave.PENABLE.value = 1
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if slave.PCLK is not None:
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await RisingEdge(slave.PCLK)
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else:
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await Timer(1, unit="ns")
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assert get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} must keep PSEL asserted"
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assert get_int(entry["outputs"]["PENABLE"], index) == 1, (
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f"{master_name} must assert PENABLE in access"
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)
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assert get_int(entry["outputs"]["PADDR"], index) == master_address, (
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f"{master_name} must keep write address stable"
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)
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assert get_int(entry["outputs"]["PWDATA"], index) == write_data, (
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f"{master_name} must keep write data stable"
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)
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assert int(slave.PREADY.value) == 1, "Slave ready should mirror selected master"
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assert int(slave.PSLVERR.value) == 0, "Write should complete without error"
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slave.PSEL.value = 0
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slave.PENABLE.value = 0
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slave.PWRITE.value = 0
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set_value(entry["inputs"]["PREADY"], index, 0)
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if slave.PCLK is not None:
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await RisingEdge(slave.PCLK)
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else:
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await Timer(1, unit="ns")
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# ------------------------------------------------------------------
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# Read phase
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# ------------------------------------------------------------------
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read_data = _read_pattern(address, config["data_width"])
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set_value(entry["inputs"]["PRDATA"], index, read_data)
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set_value(entry["inputs"]["PREADY"], index, 0)
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set_value(entry["inputs"]["PSLVERR"], index, 0)
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# ------------------------------------------------------------------
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# Setup phase
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# ------------------------------------------------------------------
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slave.PADDR.value = address
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slave.PWRITE.value = 0
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slave.PSEL.value = 1
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slave.PENABLE.value = 0
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if slave.PCLK is not None:
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await RisingEdge(slave.PCLK)
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else:
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await Timer(1, unit="ns")
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assert get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} must assert PSEL for read"
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assert get_int(entry["outputs"]["PENABLE"], index) == 0, (
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f"{master_name} must hold PENABLE low in setup"
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)
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assert get_int(entry["outputs"]["PWRITE"], index) == 0, (
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f"{master_name} should clear write during read"
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)
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assert get_int(entry["outputs"]["PADDR"], index) == master_address, (
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f"{master_name} must receive read address"
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)
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for other_name, other_idx in all_index_pairs(masters):
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if other_name == master_name and other_idx == index:
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continue
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other_entry = masters[other_name]
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assert get_int(other_entry["outputs"]["PSEL"], other_idx) == 0, (
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f"{other_name}{other_idx} must stay idle during read of {txn['label']}"
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)
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# ------------------------------------------------------------------
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# Access phase
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# ------------------------------------------------------------------
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set_value(entry["inputs"]["PREADY"], index, 1)
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slave.PENABLE.value = 1
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if slave.PCLK is not None:
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await RisingEdge(slave.PCLK)
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else:
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await Timer(1, unit="ns")
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assert get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} must keep PSEL asserted"
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assert get_int(entry["outputs"]["PENABLE"], index) == 1, (
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f"{master_name} must assert PENABLE in access"
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)
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assert int(slave.PRDATA.value) == read_data, "Read data should propagate back to the slave"
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assert int(slave.PREADY.value) == 1, "Slave ready should acknowledge the read"
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assert int(slave.PSLVERR.value) == 0, "Read should not signal an error"
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slave.PSEL.value = 0
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slave.PENABLE.value = 0
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set_value(entry["inputs"]["PREADY"], index, 0)
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set_value(entry["inputs"]["PRDATA"], index, 0)
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if slave.PCLK is not None:
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await RisingEdge(slave.PCLK)
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else:
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await Timer(1, unit="ns")
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@cocotb.test()
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async def test_apb3_invalid_address_response(dut) -> None:
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"""Ensure invalid addresses yield an error response and no master select."""
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config = load_config()
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slave = _Apb3SlaveShim(dut)
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masters = _build_master_table(dut, config["masters"])
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await start_clock(slave.PCLK)
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if slave.PRESETn is not None:
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slave.PRESETn.value = 1
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slave.PSEL.value = 0
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slave.PENABLE.value = 0
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slave.PWRITE.value = 0
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slave.PADDR.value = 0
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slave.PWDATA.value = 0
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for master_name, idx in all_index_pairs(masters):
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entry = masters[master_name]
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set_value(entry["inputs"]["PREADY"], idx, 0)
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set_value(entry["inputs"]["PSLVERR"], idx, 0)
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set_value(entry["inputs"]["PRDATA"], idx, 0)
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invalid_addr = find_invalid_address(config)
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if invalid_addr is None:
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dut._log.warning("No unmapped address found; skipping invalid address test")
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return
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slave.PADDR.value = invalid_addr
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slave.PWRITE.value = 1
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slave.PWDATA.value = _write_pattern(invalid_addr, config["data_width"])
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slave.PSEL.value = 1
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slave.PENABLE.value = 0
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if slave.PCLK is not None:
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await RisingEdge(slave.PCLK)
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else:
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await Timer(1, unit="ns")
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slave.PENABLE.value = 1
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if slave.PCLK is not None:
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await RisingEdge(slave.PCLK)
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else:
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await Timer(1, unit="ns")
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for master_name, idx in all_index_pairs(masters):
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entry = masters[master_name]
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assert get_int(entry["outputs"]["PSEL"], idx) == 0, (
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f"{master_name}{idx} must stay idle for invalid address"
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)
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assert int(slave.PREADY.value) == 1, "Invalid address should still complete the transfer"
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assert int(slave.PSLVERR.value) == 1, "Invalid address should raise PSLVERR"
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