4dc61d24ca
* Initial plan * Add cocotb test infrastructure and testbenches for APB3, APB4, and AXI4-Lite Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add integration tests, examples, and documentation for cocotb testbenches Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Address code review feedback: use relative imports and update installation docs Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add implementation summary document Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Merge cocotb dependencies into test group Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add optional cocotb simulation workflow with Icarus Verilog Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
81 lines
2.4 KiB
Python
81 lines
2.4 KiB
Python
"""Common utilities for cocotb testbenches."""
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import os
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import tempfile
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from pathlib import Path
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from tempfile import NamedTemporaryFile
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from typing import Any
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from systemrdl import RDLCompiler
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from peakrdl_busdecoder.exporter import BusDecoderExporter
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def compile_rdl_and_export(
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rdl_source: str, top_name: str, output_dir: str, cpuif_cls: Any, **kwargs: Any
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) -> tuple[Path, Path]:
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"""
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Compile RDL source and export to SystemVerilog.
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Args:
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rdl_source: SystemRDL source code as a string
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top_name: Name of the top-level addrmap
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output_dir: Directory to write generated files
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cpuif_cls: CPU interface class to use
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**kwargs: Additional arguments to pass to exporter
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Returns:
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Tuple of (module_path, package_path) for generated files
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"""
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# Compile RDL source
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compiler = RDLCompiler()
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# Write source to temporary file
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with NamedTemporaryFile("w", suffix=".rdl", dir=output_dir, delete=False) as tmp_file:
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tmp_file.write(rdl_source)
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tmp_file.flush()
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tmp_path = tmp_file.name
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try:
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compiler.compile_file(tmp_path)
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top = compiler.elaborate(top_name)
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# Export to SystemVerilog
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exporter = BusDecoderExporter()
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exporter.export(top, output_dir, cpuif_cls=cpuif_cls, **kwargs)
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finally:
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# Clean up temporary RDL file
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if os.path.exists(tmp_path):
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os.unlink(tmp_path)
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# Return paths to generated files
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module_name = kwargs.get("module_name", top_name)
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package_name = kwargs.get("package_name", f"{top_name}_pkg")
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module_path = Path(output_dir) / f"{module_name}.sv"
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package_path = Path(output_dir) / f"{package_name}.sv"
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return module_path, package_path
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def get_verilog_sources(module_path: Path, package_path: Path, intf_files: list[Path]) -> list[str]:
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"""
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Get list of Verilog source files needed for simulation.
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Args:
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module_path: Path to the generated module file
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package_path: Path to the generated package file
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intf_files: List of paths to interface definition files
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Returns:
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List of source file paths as strings
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"""
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sources = []
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# Add interface files first
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sources.extend([str(f) for f in intf_files])
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# Add package file
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sources.append(str(package_path))
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# Add module file
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sources.append(str(module_path))
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return sources
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