48 lines
1.2 KiB
ReStructuredText
48 lines
1.2 KiB
ReStructuredText
Exporter API
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============
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If you are not using the `PeakRDL command-line tool <https://peakrdl.readthedocs.io>`_,
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you can still generate busdecoders programmatically using the exporter API:
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.. autoclass:: peakrdl_busdecoder.BusDecoderExporter
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:members:
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Example
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-------
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Below is a simple example that demonstrates how to generate a SystemVerilog
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implementation from SystemRDL source.
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.. code-block:: python
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:emphasize-lines: 2-4, 29-33
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import sys
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from systemrdl import RDLCompiler, RDLCompileError
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from peakrdl_busdecoder import BusDecoderExporter
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from peakrdl_busdecoder.cpuif.axi4lite import AXI4LiteCpuif
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input_files = [
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"PATH/TO/my_register_block.rdl"
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]
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# Create an instance of the compiler
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rdlc = RDLCompiler()
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try:
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# Compile your RDL files
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for input_file in input_files:
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rdlc.compile_file(input_file)
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# Elaborate the design
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root = rdlc.elaborate()
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except RDLCompileError:
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# A compilation error occurred. Exit with error code
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sys.exit(1)
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# Export a SystemVerilog implementation
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exporter = BusDecoderExporter()
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exporter.export(
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root, "path/to/output_dir",
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cpuif_cls=AXI4LiteCpuif
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)
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