358 lines
14 KiB
Python
358 lines
14 KiB
Python
"""AXI4-Lite smoke test driven from SystemRDL-generated register maps."""
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from __future__ import annotations
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from typing import Any
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import cocotb
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from cocotb.triggers import Timer
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from tests.cocotb_lib.handle_utils import SignalHandle
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from tests.cocotb_lib.protocol_utils import (
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all_index_pairs,
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find_invalid_address,
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get_int,
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load_config,
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set_value,
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)
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class _AxilSlaveShim:
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"""Accessor for AXI4-Lite slave ports on the DUT."""
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def __init__(self, dut):
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prefix = "s_axil"
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self.AWREADY = getattr(dut, f"{prefix}_AWREADY")
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self.AWVALID = getattr(dut, f"{prefix}_AWVALID")
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self.AWADDR = getattr(dut, f"{prefix}_AWADDR")
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self.AWPROT = getattr(dut, f"{prefix}_AWPROT")
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self.WREADY = getattr(dut, f"{prefix}_WREADY")
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self.WVALID = getattr(dut, f"{prefix}_WVALID")
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self.WDATA = getattr(dut, f"{prefix}_WDATA")
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self.WSTRB = getattr(dut, f"{prefix}_WSTRB")
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self.BREADY = getattr(dut, f"{prefix}_BREADY")
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self.BVALID = getattr(dut, f"{prefix}_BVALID")
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self.BRESP = getattr(dut, f"{prefix}_BRESP")
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self.ARREADY = getattr(dut, f"{prefix}_ARREADY")
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self.ARVALID = getattr(dut, f"{prefix}_ARVALID")
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self.ARADDR = getattr(dut, f"{prefix}_ARADDR")
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self.ARPROT = getattr(dut, f"{prefix}_ARPROT")
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self.RREADY = getattr(dut, f"{prefix}_RREADY")
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self.RVALID = getattr(dut, f"{prefix}_RVALID")
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self.RDATA = getattr(dut, f"{prefix}_RDATA")
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self.RRESP = getattr(dut, f"{prefix}_RRESP")
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def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dict[str, Any]]:
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table: dict[str, dict[str, Any]] = {}
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for master in masters_cfg:
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prefix = master["port_prefix"]
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entry = {
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"indices": [tuple(idx) for idx in master["indices"]] or [tuple()],
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"outputs": {
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"AWVALID": SignalHandle(dut, f"{prefix}_AWVALID"),
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"AWADDR": SignalHandle(dut, f"{prefix}_AWADDR"),
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"AWPROT": SignalHandle(dut, f"{prefix}_AWPROT"),
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"WVALID": SignalHandle(dut, f"{prefix}_WVALID"),
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"WDATA": SignalHandle(dut, f"{prefix}_WDATA"),
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"WSTRB": SignalHandle(dut, f"{prefix}_WSTRB"),
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"ARVALID": SignalHandle(dut, f"{prefix}_ARVALID"),
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"ARADDR": SignalHandle(dut, f"{prefix}_ARADDR"),
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"ARPROT": SignalHandle(dut, f"{prefix}_ARPROT"),
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},
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"inputs": {
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"AWREADY": SignalHandle(dut, f"{prefix}_AWREADY"),
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"WREADY": SignalHandle(dut, f"{prefix}_WREADY"),
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"BVALID": SignalHandle(dut, f"{prefix}_BVALID"),
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"BRESP": SignalHandle(dut, f"{prefix}_BRESP"),
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"ARREADY": SignalHandle(dut, f"{prefix}_ARREADY"),
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"RVALID": SignalHandle(dut, f"{prefix}_RVALID"),
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"RDATA": SignalHandle(dut, f"{prefix}_RDATA"),
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"RRESP": SignalHandle(dut, f"{prefix}_RRESP"),
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},
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"inst_size": master["inst_size"],
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"inst_address": master["inst_address"],
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}
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table[master["inst_name"]] = entry
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return table
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def _write_pattern(address: int, width: int) -> int:
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mask = (1 << width) - 1
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return ((address * 0x3105) ^ 0x1357_9BDF) & mask
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def _read_pattern(address: int, width: int) -> int:
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mask = (1 << width) - 1
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return ((address ^ 0x2468_ACED) + width) & mask
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@cocotb.test()
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async def test_axi4lite_address_decoding(dut) -> None:
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"""Stimulate AXI4-Lite slave channels and verify master port selection."""
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config = load_config()
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slave = _AxilSlaveShim(dut)
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masters = _build_master_table(dut, config["masters"])
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slave.AWVALID.value = 0
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slave.AWADDR.value = 0
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slave.AWPROT.value = 0
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slave.WVALID.value = 0
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slave.WDATA.value = 0
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slave.WSTRB.value = 0
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slave.BREADY.value = 0
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slave.ARVALID.value = 0
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slave.ARADDR.value = 0
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slave.ARPROT.value = 0
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slave.RREADY.value = 0
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for master_name, idx in all_index_pairs(masters):
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entry = masters[master_name]
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set_value(entry["inputs"]["AWREADY"], idx, 0)
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set_value(entry["inputs"]["WREADY"], idx, 0)
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set_value(entry["inputs"]["BVALID"], idx, 0)
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set_value(entry["inputs"]["BRESP"], idx, 0)
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set_value(entry["inputs"]["ARREADY"], idx, 0)
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set_value(entry["inputs"]["RVALID"], idx, 0)
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set_value(entry["inputs"]["RDATA"], idx, 0)
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set_value(entry["inputs"]["RRESP"], idx, 0)
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await Timer(1, unit="ns")
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addr_mask = (1 << config["address_width"]) - 1
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strobe_mask = (1 << config["byte_width"]) - 1
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for txn in config["transactions"]:
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master_name = txn["master"]
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index = tuple(txn["index"])
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entry = masters[master_name]
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address = txn["address"] & addr_mask
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write_data = _write_pattern(address, config["data_width"])
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set_value(entry["inputs"]["BVALID"], index, 1)
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set_value(entry["inputs"]["BRESP"], index, 0)
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slave.AWADDR.value = address
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slave.AWPROT.value = 0
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slave.AWVALID.value = 1
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slave.WDATA.value = write_data
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slave.WSTRB.value = strobe_mask
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slave.WVALID.value = 1
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slave.BREADY.value = 1
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dut._log.info(
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f"Starting transaction {txn['label']} to {master_name}{index} at address 0x{address:08X}"
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)
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master_address = (address - entry["inst_address"]) % entry["inst_size"]
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await Timer(1, unit="ns")
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assert get_int(entry["outputs"]["AWVALID"], index) == 1, f"{master_name} should see AWVALID asserted"
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assert get_int(entry["outputs"]["AWADDR"], index) == master_address, (
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f"{master_name} must receive AWADDR"
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)
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assert get_int(entry["outputs"]["WVALID"], index) == 1, f"{master_name} should see WVALID asserted"
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assert get_int(entry["outputs"]["WDATA"], index) == write_data, f"{master_name} must receive WDATA"
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assert get_int(entry["outputs"]["WSTRB"], index) == strobe_mask, f"{master_name} must receive WSTRB"
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assert int(slave.AWREADY.value) == 1, "AWREADY should assert when write address/data are valid"
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assert int(slave.WREADY.value) == 1, "WREADY should assert when write address/data are valid"
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for other_name, other_idx in all_index_pairs(masters):
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if other_name == master_name and other_idx == index:
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continue
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other_entry = masters[other_name]
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assert get_int(other_entry["outputs"]["AWVALID"], other_idx) == 0, (
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f"{other_name}{other_idx} AWVALID should remain low during {txn['label']}"
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)
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assert get_int(other_entry["outputs"]["WVALID"], other_idx) == 0, (
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f"{other_name}{other_idx} WVALID should remain low during {txn['label']}"
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)
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assert int(slave.BVALID.value) == 1, "Slave should observe BVALID from selected master"
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assert int(slave.BRESP.value) == 0, "BRESP should indicate OKAY on write"
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slave.AWVALID.value = 0
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slave.WVALID.value = 0
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slave.BREADY.value = 0
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set_value(entry["inputs"]["BVALID"], index, 0)
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await Timer(1, unit="ns")
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read_data = _read_pattern(address, config["data_width"])
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set_value(entry["inputs"]["RVALID"], index, 1)
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set_value(entry["inputs"]["RDATA"], index, read_data)
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set_value(entry["inputs"]["RRESP"], index, 0)
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slave.ARADDR.value = address
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slave.ARPROT.value = 0
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slave.ARVALID.value = 1
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slave.RREADY.value = 1
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await Timer(1, unit="ns")
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assert get_int(entry["outputs"]["ARVALID"], index) == 1, f"{master_name} should assert ARVALID"
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assert get_int(entry["outputs"]["ARADDR"], index) == master_address, (
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f"{master_name} must receive ARADDR"
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)
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assert int(slave.ARREADY.value) == 1, "ARREADY should assert when ARVALID is high"
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for other_name, other_idx in all_index_pairs(masters):
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if other_name == master_name and other_idx == index:
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continue
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other_entry = masters[other_name]
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assert get_int(other_entry["outputs"]["ARVALID"], other_idx) == 0, (
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f"{other_name}{other_idx} ARVALID should remain low during read of {txn['label']}"
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)
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assert int(slave.RVALID.value) == 1, "Slave should observe RVALID when master responds"
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assert int(slave.RDATA.value) == read_data, "Read data must fold back to slave"
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assert int(slave.RRESP.value) == 0, "Read response should indicate success"
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slave.ARVALID.value = 0
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slave.RREADY.value = 0
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set_value(entry["inputs"]["RVALID"], index, 0)
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set_value(entry["inputs"]["RDATA"], index, 0)
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await Timer(1, unit="ns")
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@cocotb.test()
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async def test_axi4lite_invalid_write_handshake(dut) -> None:
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"""Ensure mismatched AW/W valid signals raise an error and are ignored."""
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config = load_config()
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slave = _AxilSlaveShim(dut)
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masters = _build_master_table(dut, config["masters"])
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slave.AWVALID.value = 0
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slave.AWADDR.value = 0
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slave.AWPROT.value = 0
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slave.WVALID.value = 0
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slave.WDATA.value = 0
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slave.WSTRB.value = 0
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slave.BREADY.value = 0
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slave.ARVALID.value = 0
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slave.ARADDR.value = 0
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slave.ARPROT.value = 0
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slave.RREADY.value = 0
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for master_name, idx in all_index_pairs(masters):
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entry = masters[master_name]
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set_value(entry["inputs"]["AWREADY"], idx, 0)
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set_value(entry["inputs"]["WREADY"], idx, 0)
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set_value(entry["inputs"]["BVALID"], idx, 0)
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set_value(entry["inputs"]["BRESP"], idx, 0)
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set_value(entry["inputs"]["ARREADY"], idx, 0)
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set_value(entry["inputs"]["RVALID"], idx, 0)
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set_value(entry["inputs"]["RDATA"], idx, 0)
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set_value(entry["inputs"]["RRESP"], idx, 0)
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await Timer(1, unit="ns")
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if not config["transactions"]:
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dut._log.warning("No transactions available; skipping invalid handshake test")
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return
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bad_addr = config["transactions"][0]["address"] & ((1 << config["address_width"]) - 1)
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slave.AWADDR.value = bad_addr
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slave.AWPROT.value = 0
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slave.AWVALID.value = 1
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slave.WVALID.value = 0
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slave.BREADY.value = 1
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await Timer(1, unit="ns")
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for master_name, idx in all_index_pairs(masters):
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entry = masters[master_name]
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assert get_int(entry["outputs"]["AWVALID"], idx) == 0, (
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f"{master_name}{idx} must not see AWVALID on invalid handshake"
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)
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assert get_int(entry["outputs"]["WVALID"], idx) == 0, (
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f"{master_name}{idx} must not see WVALID on invalid handshake"
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)
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assert int(slave.AWREADY.value) == 0, "AWREADY must remain low on invalid write handshake"
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assert int(slave.WREADY.value) == 0, "WREADY must remain low on invalid write handshake"
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assert int(slave.BVALID.value) == 1, "Invalid write handshake should return BVALID"
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assert int(slave.BRESP.value) == 2, "Invalid write handshake should return SLVERR"
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@cocotb.test()
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async def test_axi4lite_invalid_address_response(dut) -> None:
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"""Ensure unmapped addresses return error responses and do not select a master."""
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config = load_config()
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slave = _AxilSlaveShim(dut)
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masters = _build_master_table(dut, config["masters"])
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slave.AWVALID.value = 0
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slave.AWADDR.value = 0
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slave.AWPROT.value = 0
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slave.WVALID.value = 0
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slave.WDATA.value = 0
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slave.WSTRB.value = 0
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slave.BREADY.value = 0
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slave.ARVALID.value = 0
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slave.ARADDR.value = 0
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slave.ARPROT.value = 0
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slave.RREADY.value = 0
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for master_name, idx in all_index_pairs(masters):
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entry = masters[master_name]
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set_value(entry["inputs"]["AWREADY"], idx, 0)
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set_value(entry["inputs"]["WREADY"], idx, 0)
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set_value(entry["inputs"]["BVALID"], idx, 0)
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set_value(entry["inputs"]["BRESP"], idx, 0)
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set_value(entry["inputs"]["ARREADY"], idx, 0)
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set_value(entry["inputs"]["RVALID"], idx, 0)
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set_value(entry["inputs"]["RDATA"], idx, 0)
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set_value(entry["inputs"]["RRESP"], idx, 0)
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await Timer(1, unit="ns")
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invalid_addr = find_invalid_address(config)
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if invalid_addr is None:
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dut._log.warning("No unmapped address found; skipping invalid address test")
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return
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# Invalid read
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slave.ARADDR.value = invalid_addr
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slave.ARPROT.value = 0
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slave.ARVALID.value = 1
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slave.RREADY.value = 1
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await Timer(1, unit="ns")
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for master_name, idx in all_index_pairs(masters):
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entry = masters[master_name]
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assert get_int(entry["outputs"]["ARVALID"], idx) == 0, (
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f"{master_name}{idx} must stay idle for invalid read address"
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)
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assert int(slave.RVALID.value) == 1, "Invalid read should return RVALID"
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assert int(slave.RRESP.value) == 2, "Invalid read should return SLVERR"
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slave.ARVALID.value = 0
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slave.RREADY.value = 0
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await Timer(1, unit="ns")
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# Invalid write
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slave.AWADDR.value = invalid_addr
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slave.AWPROT.value = 0
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slave.AWVALID.value = 1
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slave.WDATA.value = 0xA5A5_5A5A
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slave.WSTRB.value = (1 << config["byte_width"]) - 1
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slave.WVALID.value = 1
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slave.BREADY.value = 1
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await Timer(1, unit="ns")
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for master_name, idx in all_index_pairs(masters):
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entry = masters[master_name]
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assert get_int(entry["outputs"]["AWVALID"], idx) == 0, (
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f"{master_name}{idx} must stay idle for invalid write address"
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)
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assert get_int(entry["outputs"]["WVALID"], idx) == 0, (
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f"{master_name}{idx} must stay idle for invalid write address"
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)
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assert int(slave.BVALID.value) == 1, "Invalid write should return BVALID"
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assert int(slave.BRESP.value) == 2, "Invalid write should return SLVERR"
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