104 lines
3.4 KiB
ReStructuredText
104 lines
3.4 KiB
ReStructuredText
.. _fixedpoint:
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Fixed-Point Fields
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==================
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`Fixed-point <https://en.wikipedia.org/wiki/Fixed-point_arithmetic>`_ numbers
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can be used to efficiently represent real numbers using integers. Fixed-point
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numbers consist of some combination of integer bits and fractional bits. The
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number of integer/fractional bits is usually implicitly tracked (not stored)
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for each number, unlike for floating-point numbers.
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For this SystemVerilog exporter, these properties only affect the signal type in
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the the ``hwif`` structs. There is no special handling in the internals of
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the busdecoder.
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Properties
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----------
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Fields can be declared as fixed-point numbers using the following two properties:
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.. literalinclude:: ../../hdl-src/busdecoder_udps.rdl
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:lines: 46-54
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The :ref:`is_signed<signed>` property can be used in conjunction with these
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properties to declare signed fixed-point fields.
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These UDP definitions, along with others supported by PeakRDL-busdecoder, can be
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enabled by compiling the following file along with your design:
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:download:`busdecoder_udps.rdl <../../hdl-src/busdecoder_udps.rdl>`.
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.. describe:: intwidth
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* The ``intwidth`` property defines the number of integer bits in the
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fixed-point representation (including the sign bit, if present).
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.. describe:: fracwidth
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* The ``fracwidth`` property defines the number of fractional bits in the
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fixed-point representation.
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Representable Numbers
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^^^^^^^^^^^^^^^^^^^^^
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The range of representable real numbers is summarized in the table below.
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.. list-table:: Representable Numbers
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:header-rows: 1
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* - Signedness
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- Minimum Value
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- Maximum Value
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- Step Size
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* - Unsigned
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- :math:`0`
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- :math:`2^{\mathrm{intwidth}} - 2^{-\mathrm{fracwidth}}`
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- :math:`2^{-\mathrm{fracwidth}}`
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* - Signed
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- :math:`-2^{\mathrm{intwidth}-1}`
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- :math:`2^{\mathrm{intwidth}-1} - 2^{-\mathrm{fracwidth}}`
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- :math:`2^{-\mathrm{fracwidth}}`
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SystemVerilog Types
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^^^^^^^^^^^^^^^^^^^
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When either ``intwidth`` or ``fracwidth`` are defined for a field, that field's
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type in the generated SystemVerilog ``hwif`` struct is
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``logic (signed) [intwidth-1:-fracwidth]``. The bit at index :math:`i` contributes
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a weight of :math:`2^i` to the real number represented.
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Other Rules
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^^^^^^^^^^^
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* Only one of ``intwidth`` or ``fracwidth`` need be defined. The other is
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inferred from the field bit width.
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* The bit width of the field shall be equal to ``intwidth`` + ``fracwidth``.
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* If both ``intwidth`` and ``fracwidth`` are defined for a field, it is an
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error if their sum does not equal the bit width of the field.
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* Either ``fracwidth`` or ``intwidth`` can be a negative integer. Because
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SystemRDL does not have a signed integer type, the only way to achieve
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this is to define one of the widths as larger than the bit width of the
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component so that the other width is inferred as a negative number.
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* The properties defined above are mutually exclusive with the ``counter``
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property.
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* The properties defined above are mutually exclusive with the ``encode``
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property.
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Examples
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--------
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A 12-bit signed fixed-point field with 4 integer bits and 8 fractional bits
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can be declared with
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.. code-block:: systemrdl
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:emphasize-lines: 3, 4
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field {
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sw=rw; hw=r;
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intwidth = 4;
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is_signed;
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} fixedpoint_num[11:0] = 0;
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This field can represent values from -8.0 to 7.99609375
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in steps of 0.00390625.
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