184 lines
6.5 KiB
ReStructuredText
184 lines
6.5 KiB
ReStructuredText
.. _write_buffering:
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Write-buffered Registers
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========================
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In order to support larger software write accesses that are atomic, the
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busdecoder generator understands several UDPs that implement write-buffering to
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specific registers. This causes the busdecoder to delay the effect of a software
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write operation until a defined trigger event.
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Some examples of when this is useful:
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* You need to have software update a wide 64-bit register atomically, but
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the CPU interface is only 32-bits.
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* Software needs to be able to write multiple registers such that the
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hardware is updated atomically.
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* Software can pre-load one or more registers with their next value, and
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trigger the update via an external hardware signal.
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If a register is write-buffered, a holding buffer stage is inserted between the
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decode logic and the field logic. This effectively defers any software write
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operations to that register until a trigger event occurs that releases it.
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Write buffering storage is unique to each register that enables it.
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If a register is not write buffered, this buffer stage is bypassed.
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.. figure:: ../diagrams/wbuf.png
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Properties
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----------
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The behavior of write-buffered registers is defined using the following two
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properties:
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.. literalinclude:: ../../hdl-src/busdecoder_udps.rdl
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:lines: 20-28
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These UDP definitions, along with others supported by PeakRDL-busdecoder can be
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enabled by compiling the following file along with your design:
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:download:`busdecoder_udps.rdl <../../hdl-src/busdecoder_udps.rdl>`.
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.. describe:: buffer_writes
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* Assigned value is a boolean.
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* If true, enables double-buffering of writes to this register.
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* Any software write operation to a buffered register is held back in a
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storage element unique to the register.
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* The software write operation is committed to the register once triggered
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to do so.
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* Unless specified otherwise, the buffer trigger occurs when the highest
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address of the buffered register is written.
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.. describe:: wbuffer_trigger
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* Assigned value is a reference to a register, single-bit field, signal,
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or single-bit property.
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* Controls when the double-buffer commits the software write operation to
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the register's fields.
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* If reference is a single-bit value (signal, field, property reference),
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then the assertion of that value triggers the buffer to be evicted.
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* Signal references shall have either activehigh/activelow property set to
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define the polarity.
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* If the reference is a reg, then buffer is evicted when the register's
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highest address is written.
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Other Rules
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^^^^^^^^^^^
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* It is an error to set ``buffer_writes`` if the register does not contain any
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writable fields
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* If ``buffer_writes`` is false, then anything assigned to ``wbuffer_trigger``
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is ignored.
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* The buffered register and the trigger reference shall both be within the
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same internal device. ie: one cannot be in an external scope with respect to
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the other.
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* Unless it is a register, the reference assigned to ``wbuffer_trigger`` shall
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represent a single bit.
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* If a buffered register was not written, any trigger events are ignored.
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* It is valid for a buffered register to be partially written (either via
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write strobes, or partial addressing).
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* The software write operation is not considered to take place until the
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buffer is evicted by the trigger. This influences the behavior of properties
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like ``swmod`` and ``swacc`` - they are not asserted until the register's
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fields are actually written by the buffer.
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Examples
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--------
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Below are several examples of what you can do with registers that are
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write-buffered.
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Wide Atomic Register
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^^^^^^^^^^^^^^^^^^^^
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Without write-buffering, it is impossible to update the state of a 64-bit
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register using a 32-bit CPU interface in a single clock-cycle.
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In this example, it still requires two write-cycles to update the register, but
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the register's storage element is not updated until both sub-words are written.
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Upon writing the 2nd sub-word (the higher byte address), the write data for both
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write cycles are committed to the register's storage element together on the
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same clock cycle. The register is updated atomically.
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.. code-block:: systemrdl
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:emphasize-lines: 4
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reg {
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regwidth = 64;
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accesswidth = 32;
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buffer_writes = true;
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field {
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sw=rw; hw=r;
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} my_field[63:0] = 0;
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};
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Atomic Group of Registers
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^^^^^^^^^^^^^^^^^^^^^^^^^
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Perhaps you have a group of registers that need their state to be updated
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atomically. Using the ``wbuffer_trigger`` property, you can define which
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register write operation triggers the group to be updated.
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.. code-block:: systemrdl
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:emphasize-lines: 2, 18-20
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reg my_buffered_reg {
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buffer_writes = true;
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field {
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sw=rw; hw=r;
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} my_field[31:0] = 0;
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};
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my_buffered_reg reg1;
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my_buffered_reg reg2;
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my_buffered_reg reg3;
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reg {
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field {
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sw=rw; hw=r;
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} my_field[31:0] = 0;
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} reg4;
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reg1->wbuffer_trigger = reg4;
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reg2->wbuffer_trigger = reg4;
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reg3->wbuffer_trigger = reg4;
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In this example software may pre-write information into reg1-reg3, but the
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register write operations do not take effect until software also writes to reg4.
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The write operation to reg4 triggers the buffered data to be committed to
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reg1-reg3. This is guaranteed to occur on the same clock-cycle.
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Externally Triggered Register Update
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Some applications may require precise timing for when a register (or group of
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registers) update their value. Often software cannot offer such timing
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precision.
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In this example, the trigger event is bound to an external signal. When
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asserted, any pending write operation the buffered register will be committed.
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The hwif_out value presents the new register state on the clock cycle after the
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trigger is asserted.
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.. code-block:: systemrdl
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:emphasize-lines: 2, 11-13
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reg my_buffered_reg {
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buffer_writes = true;
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field {
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sw=rw; hw=r;
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} my_field[31:0] = 0;
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};
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my_buffered_reg reg1;
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my_buffered_reg reg2;
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signal {
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activehigh;
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} trigger_signal;
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reg1->wbuffer_trigger = trigger_signal;
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reg2->wbuffer_trigger = trigger_signal;
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After software writes to ``reg1`` & ``reg2``, the written data is held back in
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the write buffer until ``hwif_in..trigger_signal`` is asserted by the hardware.
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