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* Initial plan * Add cocotb test infrastructure and testbenches for APB3, APB4, and AXI4-Lite Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add integration tests, examples, and documentation for cocotb testbenches Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Address code review feedback: use relative imports and update installation docs Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add implementation summary document Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Merge cocotb dependencies into test group Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add optional cocotb simulation workflow with Icarus Verilog Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
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Cocotb Integration Tests
This directory contains cocotb-based integration tests that verify the functionality of generated bus decoder RTL for different CPU interfaces.
Overview
These tests:
- Generate SystemVerilog decoder modules from SystemRDL specifications
- Simulate the generated RTL using cocotb
- Verify read/write operations work correctly for different bus protocols
Supported CPU Interfaces
- APB3 (AMBA APB3)
- APB4 (AMBA APB4 with strobe support)
- AXI4-Lite (AMBA AXI4-Lite)
Running the Tests
Install Dependencies
# Using uv (recommended)
uv sync --group test
# Or using pip
pip install -e .[test]
Run All Cocotb Tests
pytest tests/cocotb/testbenches/
Run Specific Interface Tests
# Test APB4 interface
pytest tests/cocotb/testbenches/test_apb4_decoder.py
# Test APB3 interface
pytest tests/cocotb/testbenches/test_apb3_decoder.py
# Test AXI4-Lite interface
pytest tests/cocotb/testbenches/test_axi4lite_decoder.py
Test Structure
common/: Shared utilities and base classes for cocotb teststestbenches/: Individual testbenches for each CPU interface