4dc61d24ca
* Initial plan * Add cocotb test infrastructure and testbenches for APB3, APB4, and AXI4-Lite Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add integration tests, examples, and documentation for cocotb testbenches Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Address code review feedback: use relative imports and update installation docs Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add implementation summary document Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Merge cocotb dependencies into test group Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add optional cocotb simulation workflow with Icarus Verilog Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
124 lines
3.3 KiB
Python
124 lines
3.3 KiB
Python
"""APB4 Master Bus Functional Model for cocotb."""
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import cocotb
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from cocotb.triggers import RisingEdge, Timer
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class APB4Master:
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"""APB4 Master Bus Functional Model."""
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def __init__(self, dut, name, clock):
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"""
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Initialize APB4 Master.
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Args:
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dut: The device under test
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name: Signal name prefix (e.g., 's_apb')
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clock: Clock signal to use for synchronization
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"""
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self.dut = dut
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self.clock = clock
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self.name = name
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# Get signals
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self.psel = getattr(dut, f"{name}_PSEL")
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self.penable = getattr(dut, f"{name}_PENABLE")
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self.pwrite = getattr(dut, f"{name}_PWRITE")
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self.paddr = getattr(dut, f"{name}_PADDR")
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self.pwdata = getattr(dut, f"{name}_PWDATA")
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self.pstrb = getattr(dut, f"{name}_PSTRB")
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self.pprot = getattr(dut, f"{name}_PPROT")
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self.prdata = getattr(dut, f"{name}_PRDATA")
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self.pready = getattr(dut, f"{name}_PREADY")
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self.pslverr = getattr(dut, f"{name}_PSLVERR")
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def reset(self):
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"""Reset the bus to idle state."""
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self.psel.value = 0
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self.penable.value = 0
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self.pwrite.value = 0
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self.paddr.value = 0
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self.pwdata.value = 0
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self.pstrb.value = 0
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self.pprot.value = 0
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async def write(self, addr, data, strb=None):
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"""
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Perform APB4 write transaction.
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Args:
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addr: Address to write to
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data: Data to write
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strb: Byte strobe mask (default: all bytes enabled)
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Returns:
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True if write succeeded, False if error
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"""
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# Calculate strobe if not provided
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if strb is None:
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data_width_bytes = len(self.pwdata) // 8
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strb = (1 << data_width_bytes) - 1
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# Setup phase
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await RisingEdge(self.clock)
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self.psel.value = 1
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self.penable.value = 0
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self.pwrite.value = 1
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self.paddr.value = addr
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self.pwdata.value = data
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self.pstrb.value = strb
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self.pprot.value = 0
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# Access phase
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await RisingEdge(self.clock)
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self.penable.value = 1
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# Wait for ready
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while True:
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await RisingEdge(self.clock)
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if self.pready.value == 1:
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error = self.pslverr.value == 1
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break
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# Return to idle
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self.psel.value = 0
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self.penable.value = 0
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return not error
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async def read(self, addr):
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"""
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Perform APB4 read transaction.
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Args:
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addr: Address to read from
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Returns:
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Tuple of (data, error) where error is True if read failed
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"""
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# Setup phase
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await RisingEdge(self.clock)
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self.psel.value = 1
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self.penable.value = 0
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self.pwrite.value = 0
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self.paddr.value = addr
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self.pprot.value = 0
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# Access phase
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await RisingEdge(self.clock)
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self.penable.value = 1
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# Wait for ready
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while True:
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await RisingEdge(self.clock)
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if self.pready.value == 1:
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data = self.prdata.value.integer
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error = self.pslverr.value == 1
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break
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# Return to idle
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self.psel.value = 0
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self.penable.value = 0
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return data, error
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