95fda3abaa
* Initial plan * Refactor cpuif classes to use Interface abstraction Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix type annotation consistency in Interface.signal() Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add runtime validation and documentation for indexer types Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Remove unused variable in SVInterface.signal() Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix master port directions in APB3 and APB4 flat interfaces Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix AXI4LiteCpuifFlat and apply code formatting Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * PSELx -> PSEL * cleanup marker warnings --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
69 lines
2.3 KiB
Python
69 lines
2.3 KiB
Python
from typing import TYPE_CHECKING
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from systemrdl.node import AddressableNode
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from ...utils import get_indexed_path
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from ..base_cpuif import BaseCpuif
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from .apb3_interface import APB3FlatInterface
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if TYPE_CHECKING:
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from ...exporter import BusDecoderExporter
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class APB3CpuifFlat(BaseCpuif):
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template_path = "apb3_tmpl.sv"
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def __init__(self, exp: "BusDecoderExporter") -> None:
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super().__init__(exp)
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self._interface = APB3FlatInterface(self)
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@property
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def is_interface(self) -> bool:
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return self._interface.is_interface
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@property
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def port_declaration(self) -> str:
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return self._interface.get_port_declaration("s_apb_", "m_apb_")
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def signal(
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self,
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signal: str,
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node: AddressableNode | None = None,
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idx: str | int | None = None,
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) -> str:
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return self._interface.signal(signal, node, idx)
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def fanout(self, node: AddressableNode) -> str:
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fanout: dict[str, str] = {}
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fanout[self.signal("PSEL", node)] = (
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f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}"
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)
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fanout[self.signal("PENABLE", node)] = self.signal("PENABLE")
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fanout[self.signal("PWRITE", node)] = (
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f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}"
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)
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fanout[self.signal("PADDR", node)] = self.signal("PADDR")
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fanout[self.signal("PWDATA", node)] = "cpuif_wr_data"
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return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
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def fanin(self, node: AddressableNode | None = None) -> str:
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fanin: dict[str, str] = {}
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if node is None:
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fanin["cpuif_rd_ack"] = "'0"
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fanin["cpuif_rd_err"] = "'0"
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else:
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fanin["cpuif_rd_ack"] = self.signal("PREADY", node)
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fanin["cpuif_rd_err"] = self.signal("PSLVERR", node)
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return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
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def readback(self, node: AddressableNode | None = None) -> str:
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fanin: dict[str, str] = {}
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if node is None:
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fanin["cpuif_rd_data"] = "'0"
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else:
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fanin["cpuif_rd_data"] = self.signal("PRDATA", node)
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return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
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