34 lines
1.2 KiB
ReStructuredText
34 lines
1.2 KiB
ReStructuredText
Intel Avalon
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============
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Implements the register block using an
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`Intel Avalon MM <https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/memory-mapped-interfaces.html>`_
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CPU interface.
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The Avalon interface comes in two i/o port flavors:
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SystemVerilog Interface
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* Command line: ``--cpuif avalon-mm``
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* Interface Definition: :download:`avalon_mm_intf.sv <../../hdl-src/avalon_mm_intf.sv>`
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* Class: :class:`peakrdl_regblock.cpuif.avalon.Avalon_Cpuif`
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Flattened inputs/outputs
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Flattens the interface into discrete input and output ports.
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* Command line: ``--cpuif avalon-mm-flat``
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* Class: :class:`peakrdl_regblock.cpuif.avalon.Avalon_Cpuif_flattened`
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Implementation Details
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----------------------
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This implementation of the Avalon protocol has the following features:
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* Interface uses word addressing.
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* Supports `pipelined transfers <https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/pipelined-transfers.html>`_
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* Responses may have variable latency
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In most cases, latency is fixed and is determined by how many retiming
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stages are enabled in your design.
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However if your design contains external components, access latency is
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not guaranteed to be uniform.
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