33 lines
1.2 KiB
ReStructuredText
33 lines
1.2 KiB
ReStructuredText
.. _cpuif_axi4lite:
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AMBA AXI4-Lite
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==============
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Implements the register block using an
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`AMBA AXI4-Lite <https://developer.arm.com/documentation/ihi0022/e/AMBA-AXI4-Lite-Interface-Specification>`_
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CPU interface.
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The AXI4-Lite CPU interface comes in two i/o port flavors:
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SystemVerilog Interface
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* Command line: ``--cpuif axi4-lite``
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* Interface Definition: :download:`axi4lite_intf.sv <../../hdl-src/axi4lite_intf.sv>`
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* Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif`
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Flattened inputs/outputs
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Flattens the interface into discrete input and output ports.
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* Command line: ``--cpuif axi4-lite-flat``
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* Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif_flattened`
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Pipelined Performance
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---------------------
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This implementation of the AXI4-Lite interface supports transaction pipelining
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which can significantly improve performance of back-to-back transfers.
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In order to support transaction pipelining, the CPU interface will accept multiple
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concurrent transactions. The number of outstanding transactions allowed is automatically
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determined based on the register file pipeline depth (affected by retiming options),
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and influences the depth of the internal transaction response skid buffer.
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