54 lines
1.5 KiB
ReStructuredText
54 lines
1.5 KiB
ReStructuredText
Known Limitations
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=================
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Not all SystemRDL features are supported by this exporter. For a listing of
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supported properties, see the appropriate property listing page in the sections
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that follow.
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Alias Registers
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---------------
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Registers instantiated using the ``alias`` keyword are not supported yet.
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Unaligned Registers
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-------------------
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All address offsets & strides shall be a multiple of the cpuif bus width used. Specifically:
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* Bus width is inferred by the maximum accesswidth used in the regblock.
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* Each component's address and array stride shall be aligned to the bus width.
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Uniform accesswidth
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-------------------
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All registers within a register block shall use the same accesswidth.
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One exception is that registers with regwidth that is narrower than the cpuif
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bus width are permitted, provided that their regwidth is equal to their accesswidth.
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For example:
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.. code-block:: systemrdl
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// (Largest accesswidth used is 32, therefore the CPUIF bus width is 32)
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reg {
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regwidth = 32;
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accesswidth = 32;
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} reg_a @ 0x00; // OK. Regular 32-bit register
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reg {
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regwidth = 64;
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accesswidth = 32;
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} reg_b @ 0x08; // OK. "Wide" register of 64-bits, but is accessed using 32-bit subwords
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reg {
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regwidth = 8;
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accesswidth = 8;
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} reg_c @ 0x10; // OK. Is aligned to the cpuif bus width
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reg {
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regwidth = 32;
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accesswidth = 8;
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} bad_reg @ 0x14; // NOT OK. accesswidth conflicts with cpuif width
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