492 lines
13 KiB
ReStructuredText
492 lines
13 KiB
ReStructuredText
Field Properties
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================
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.. note:: Any properties not explicitly listed here are either implicitly
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supported, or are not relevant to the regblock exporter and are ignored.
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Software Access Properties
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--------------------------
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onread/onwrite
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^^^^^^^^^^^^^^
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All onread/onwrite actions are supported (except for ruser/wuser)
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rclr/rset
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^^^^^^^^^
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See ``onread``. These are effectively aliases of the onread property.
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singlepulse
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^^^^^^^^^^^
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If set, field will get cleared back to zero after being written.
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.. wavedrom::
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{"signal": [
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{"name": "clk", "wave": "p....."},
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{"name": "<swmod>", "wave": "0.10.."},
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{"name": "hwif_out..value", "wave": "0..10."}
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]}
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sw
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^^^
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All sw access modes are supported except for ``w1`` and ``rw1``.
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swacc
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^^^^^
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If true, infers an output signal ``hwif_out..swacc`` that is asserted when
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accessed by software. Specifically, on the same clock cycle that the field is
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being sampled during a software read operation, or as it is being written.
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.. wavedrom::
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{"signal": [
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{"name": "clk", "wave": "p...."},
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{"name": "hwif_in..next", "wave": "x.=x.", "data": ["D"]},
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{"name": "hwif_out..swacc", "wave": "0.10."}
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]}
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swmod
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^^^^^
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If true, infers an output signal ``hwif_out..swmod`` that is asserted as the
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field is being modified by software. This can be due to a software write
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operation, or a software read operation that has clear/set side-effects.
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.. wavedrom::
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{"signal": [
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{"name": "clk", "wave": "p....."},
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{"name": "hwif_out..value", "wave": "=..=..", "data": ["old", "new"]},
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{"name": "hwif_out..swmod", "wave": "0.10.."}
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]}
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swwe/swwel
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^^^^^^^^^^
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Provides a mechanism that allows hardware to override whether the field is
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writable by software.
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boolean
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If True, infers an input signal ``hwif_in..swwe`` or ``hwif_in..swwel``.
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reference
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Single-bit reference controls field's behavior.
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woclr/woset
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^^^^^^^^^^^
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See ``onwrite``. These are effectively aliases of the onwrite property.
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--------------------------------------------------------------------------------
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Hardware Access Properties
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--------------------------
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anded/ored/xored
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^^^^^^^^^^^^^^^^
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If true, infers the existence of output signal: ``hwif_out..anded``,
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``hwif_out..ored``, ``hwif_out..xored``
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hw
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^^^
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Controls hardware access to the field.
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If readable, enables output signal ``hwif_out..value``. If writable, enables
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input ``hwif_in..next``.
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Hardware-writable fields can optionally define the ``next`` property which replaces
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the inferred ``hwif_in..next`` input with an alternate reference.
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hwclr/hwset
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^^^^^^^^^^^
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If both ``hwclr`` and ``hwset`` properties are used, and both are asserted at
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the same clock cycle, then ``hwset`` will take precedence.
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boolean
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If true, infers the existence of input signal: ``hwif_in..hwclr``, ``hwif_in..hwset``
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reference
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Reference to any single-bit internal object to drive this control.
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hwenable/hwmask
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^^^^^^^^^^^^^^^
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Reference to a component that provides bit-level control of hardware writeability.
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we/wel
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^^^^^^
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Write-enable control from hardware interface.
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If true, infers the existence of input signal: ``hwif_in..we``, ``hwif_in..wel``
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.. wavedrom::
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{"signal": [
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{"name": "clk", "wave": "p...."},
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{"name": "hwif_in..next", "wave": "x.=x.", "data": ["D"]},
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{"name": "hwif_in..we", "wave": "0.10."},
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{"name": "hwif_in..wel", "wave": "1.01."},
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{"name": "<field value>", "wave": "x..=.", "data": ["D"]}
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]}
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boolean
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If true, infers the existence of input signal ``hwif_in..we`` or ``hwif_in..wel``
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reference
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Reference to any single-bit internal object to drive this control.
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--------------------------------------------------------------------------------
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Counter Properties
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------------------
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counter
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^^^^^^^
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If true, marks this field as a counter. The counter direction is inferred based
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based on which properties are assigned. By default, an up-counter is implemented.
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If any of the properties associated with an up-counter are used, then up-counting
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capabilities will be implemented. The same is true for down-counters and up/down
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counters.
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Unless alternate control signals are specified, the existence of input signals
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``hwif_in..incr`` and ``hwif_in..decr`` will be inferred depending on the type
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of counter described.
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incr
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^^^^
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Assign a reference to an alternate control signal to increment the counter.
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If assigned, the inferred ``hwif_in..incr`` input will not be generated.
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incrsaturate/saturate
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^^^^^^^^^^^^^^^^^^^^^
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If assigned, indicates that the counter will saturate instead of wrapping.
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If an alternate saturation point is specified, the counter value will be
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adjusted so that it does not exceed that limit, even after non-increment actions.
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boolean
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If true, saturation point is at the counter's maximum count value. (2^width - 1)
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integer
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Specify a static saturation value.
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reference
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Specify a dynamic saturation value.
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incrthreshold/threshold
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^^^^^^^^^^^^^^^^^^^^^^^
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If assigned, infers a ``hwif_out..incrthreshold`` output signal. This signal is
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asserted if the counter value is greater or equal to the threshold.
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.. wavedrom::
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{
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"signal": [
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{"name": "clk", "wave": "p......"},
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{"name": "hwif_in..incr", "wave": "01...0."},
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{"name": "<counter>", "wave": "=.=3==..", "data": [4,5,6,7,8,9]},
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{"name": "hwif_out..incrthreshold", "wave": "0..1...."}
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],
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"foot": {
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"text": "Example where incrthreshold = 6"
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}
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}
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boolean
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If true, threshold is the counter's maximum count value. (2^width - 1)
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integer
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Specify a static threshold value.
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reference
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Specify a dynamic threshold value.
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incrvalue
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^^^^^^^^^
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Override the counter's increment step size.
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integer
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Specify a static increment step size.
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reference
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Reference a component that controls the step size.
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incrwidth
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^^^^^^^^^
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If assigned, infers an input signal ``hwif_in..incrvalue``. The value of this
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property defines the signal's width.
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overflow
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^^^^^^^^
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If true, infers an output signal ``hwif_out..overflow`` that is asserted when
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the counter is about to wrap.
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.. wavedrom::
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{
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"signal": [
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{"name": "clk", "wave": "p......."},
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{"name": "hwif_in..incr", "wave": "0101010."},
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{"name": "<counter>", "wave": "=.=.=.=.", "data": [14,15,0,1]},
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{"name": "hwif_out..overflow", "wave": "0..10..."}
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],
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"foot": {
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"text": "A 4-bit counter overflowing"
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}
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}
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decr
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^^^^
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Assign a reference to an alternate control signal to decrement the counter.
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If assigned, the inferred ``hwif_in..decr`` input will not be generated.
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decrsaturate
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^^^^^^^^^^^^
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If assigned, indicates that the counter will saturate instead of wrapping.
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If an alternate saturation point is specified, the counter value will be
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adjusted so that it does not exceed that limit, even after non-decrement actions.
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boolean
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If true, saturation point is when the counter reaches 0.
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integer
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Specify a static saturation value.
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reference
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Specify a dynamic saturation value.
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decrthreshold
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^^^^^^^^^^^^^
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If assigned, infers a ``hwif_out..decrthreshold`` output signal. This signal is
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asserted if the counter value is less than or equal to the threshold.
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.. wavedrom::
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{
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"signal": [
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{"name": "clk", "wave": "p......"},
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{"name": "hwif_in..decr", "wave": "01...0."},
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{"name": "<counter>", "wave": "=.=3==.", "data": [9,8,7,6,5,4]},
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{"name": "hwif_out..decrthreshold", "wave": "0..1..."}
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],
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"foot": {
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"text": "Example where incrthreshold = 7"
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}
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}
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boolean
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If true, threshold is 0.
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integer
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Specify a static threshold value.
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reference
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Specify a dynamic threshold value.
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decrvalue
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^^^^^^^^^
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Override the counter's decrement step size.
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integer
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Specify a static step size.
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reference
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Reference to a component that controls the step size.
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decrwidth
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^^^^^^^^^
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If assigned, infers an input signal ``hwif_in..decrvalue``. The value of this
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property defines the signal's width.
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underflow
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^^^^^^^^^
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If true, infers an output signal ``hwif_out..underflow`` that is asserted when
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the counter is about to wrap.
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.. wavedrom::
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{
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"signal": [
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{"name": "clk", "wave": "p......."},
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{"name": "hwif_in..decr", "wave": "0101010."},
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{"name": "<counter>", "wave": "=.=.=.=.", "data": [1,0,15,14]},
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{"name": "hwif_out..underflow", "wave": "0..10..."}
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],
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"foot": {
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"text": "A 4-bit counter underflowing"
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}
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}
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--------------------------------------------------------------------------------
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Interrupt Properties
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--------------------
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intr
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^^^^
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If set, this field becomes an interrupt field.
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The enclosing register infers an output signal ``hwif_out..intr`` which denotes
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that an interrupt is active. This is an or-reduction of all interrupt fields
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after applying the appropriate ``enable`` or ``mask`` to the field value.
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level (default)
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Interrupt is level-sensitive. If a bit on the field's ``hwif_in..next`` input
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is '1', it will trigger an interrupt event.
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posedge
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If a bit on the field's ``hwif_in..next`` input transitions from '0' to '1',
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it will trigger an interrupt event. This transition shall still be synchronous
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to the register block's clock.
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negedge
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If a bit on the field's ``hwif_in..next`` input transitions from '1' to '0',
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it will trigger an interrupt event. This transition shall still be synchronous
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to the register block's clock.
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bothedge
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If a bit on the field's ``hwif_in..next`` input transitions from '0' to '1' or '1' to '0',
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it will trigger an interrupt event. This transition shall still be synchronous
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to the register block's clock.
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nonsticky
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Interrupt event is not sticky.
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enable
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^^^^^^
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Reference to a field or signal that, if set to 1, define which bits in the field
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are used to assert an interrupt.
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mask
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^^^^
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Reference to a field or signal that, if set to 1, define which bits in the field
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are *not* used to assert an interrupt.
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haltenable
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^^^^^^^^^^
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Reference to a field or signal that, if set to 1, define which bits in the field
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are used to assert the halt output.
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If this property is set, the enclosing register will infer a ``hwif_out..halt`` output.
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haltmask
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^^^^^^^^
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Reference to a field or signal that, if set to 1, define which bits in the field
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are *not* used to assert the halt output.
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If this property is set, the enclosing register will infer a ``hwif_out..halt`` output.
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stickybit
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^^^^^^^^^
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When an interrupt trigger occurs, a stickybit field will set the corresponding
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bit to '1' and hold it until it is cleared by a software access.
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The interrupt trigger depends on the interrupt type. By default, interrupts are
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level-sensitive, but the interrupt modifiers allow for edge-sensitive triggers as
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well.
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The waveform below demonstrates a level-sensitive interrupt:
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.. wavedrom::
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{
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"signal": [
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{"name": "clk", "wave": "p....."},
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{"name": "hwif_in..next", "wave": "010..."},
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{"name": "<field value>", "wave": "0.1..."}
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]
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}
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sticky
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^^^^^^
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Unlike ``stickybit`` fields, a sticky field will latch an entire value. The
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value is latched as soon as ``hwif_in..next`` is nonzero, and is held until the
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field contents are cleared back to 0 by a software access.
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.. wavedrom::
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{
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"signal": [
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{"name": "clk", "wave": "p....."},
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{"name": "hwif_in..next", "wave": "23.22.", "data": [0,10,20,30]},
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{"name": "<field value>", "wave": "2.3...", "data": [0, 10]}
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]
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}
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--------------------------------------------------------------------------------
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Misc
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----
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encode
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^^^^^^
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If assigned a user-defined enumeration, the resulting package file will include
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its definition. Due to limitations from type-strictness rules in SystemVerilog,
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the field will remain as a ``logic`` datatype.
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next
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^^^^
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If assigned, replaces the inferred ``hwif_in..next`` input with an explicit reference.
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paritycheck
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^^^^^^^^^^^
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If set, enables parity checking for this field.
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Adds a ``parity_error`` output signal to the module.
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.. note::
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If this field does not implement storage, the ``partycheck`` property is ignored.
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precedence
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^^^^^^^^^^
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Control whether hardware or software has precedence when field value update
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contention occurs. Software has precedence by default.
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reset
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^^^^^
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Control the reset value of the field's storage element.
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If not specified, the field will not be reset.
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integer
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Static reset value
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reference
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Reference to a dynamic reset value.
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resetsignal
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^^^^^^^^^^^
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Provide an alternate reset trigger for this field.
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