75 lines
2.0 KiB
ReStructuredText
75 lines
2.0 KiB
ReStructuredText
.. _signed:
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Signed Fields
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=============
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SystemRDL does not natively provide a way to mark fields as signed or unsigned.
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The ``is_signed`` user-defined property fills this need.
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For this SystemVerilog exporter, marking a field as signed only affects the
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signal type in the ``hwif`` structs. There is no special handling in the internals
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of the regblock.
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Properties
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----------
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A field can be marked as signed using the following user-defined property:
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.. literalinclude:: ../../hdl-src/regblock_udps.rdl
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:lines: 40-44
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This UDP definition, along with others supported by PeakRDL-regblock, can be
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enabled by compiling the following file along with your design:
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:download:`regblock_udps.rdl <../../hdl-src/regblock_udps.rdl>`.
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.. describe:: is_signed
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* Assigned value is a boolean.
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* If true, the hardware interface field will have the type
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``logic signed [width-1:0]``.
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* If false or not defined for a field, the hardware interface field will
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have the type ``logic [width-1:0]``, which is unsigned by definition.
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Other Rules
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^^^^^^^^^^^
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* ``is_signed=true`` is mutually exclusive with the ``counter`` property.
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* ``is_signed=true`` is mutually exclusive with the ``encode`` property.
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Examples
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--------
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Below are some examples of fields with different signedness.
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Signed Fields
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^^^^^^^^^^^^^
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.. code-block:: systemrdl
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:emphasize-lines: 3, 8
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field {
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sw=rw; hw=r;
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is_signed;
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} signed_num[63:0] = 0;
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field {
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sw=r; hw=w;
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is_signed = true;
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} another_signed_num[19:0] = 20'hFFFFF; // -1
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SystemRDL's own integer type is always unsigned. In order to specify a negative
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reset value, the two's complement value must be used as shown in the second
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example above.
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Unsigned Fields
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^^^^^^^^^^^^^^^
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.. code-block:: systemrdl
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:emphasize-lines: 3, 8
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field {
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sw=rw; hw=r;
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// fields are unsigned by default
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} unsigned_num[63:0] = 0;
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field {
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sw=r; hw=w;
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is_signed = false;
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} another_unsigned_num[19:0] = 0;
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