55 lines
941 B
Plaintext
55 lines
941 B
Plaintext
/*
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* This file defines several property extensions that are understood by the
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* PeakRDL-Regblock SystemVerilog code generator.
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*
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* Compile this file prior to your other SystemRDL sources.
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*
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* For more details, see: https://peakrdl-regblock.readthedocs.io/en/latest/udps/intro.html
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*/
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property buffer_reads {
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component = reg;
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type = boolean;
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};
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property rbuffer_trigger {
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component = reg;
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type = ref;
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};
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property buffer_writes {
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component = reg;
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type = boolean;
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};
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property wbuffer_trigger {
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component = reg;
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type = ref;
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};
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property rd_swacc {
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component = field;
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type = boolean;
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};
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property wr_swacc {
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component = field;
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type = boolean;
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};
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property is_signed {
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type = boolean;
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component = field;
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default = true;
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};
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property intwidth {
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type = longint unsigned;
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component = field;
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};
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property fracwidth {
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type = longint unsigned;
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component = field;
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};
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