52 lines
1.5 KiB
TOML
52 lines
1.5 KiB
TOML
[build-system]
|
|
requires = ["setuptools", "setuptools-scm"]
|
|
build-backend = "setuptools.build_meta"
|
|
|
|
[project]
|
|
name = "peakrdl-regblock"
|
|
dynamic = ["version"]
|
|
requires-python = ">=3.7"
|
|
dependencies = [
|
|
"systemrdl-compiler ~= 1.29",
|
|
"Jinja2>=2.11",
|
|
]
|
|
|
|
authors = [
|
|
{name="Alex Mykyta"},
|
|
]
|
|
description = "Compile SystemRDL into a SystemVerilog control/status register (CSR) block"
|
|
readme = "README.md"
|
|
license = {text = "LGPLv3"}
|
|
keywords = [
|
|
"SystemRDL", "PeakRDL", "CSR", "compiler", "tool", "registers", "generator",
|
|
"Verilog", "SystemVerilog", "register abstraction layer",
|
|
"FPGA", "ASIC",
|
|
]
|
|
classifiers = [
|
|
"Development Status :: 5 - Production/Stable",
|
|
"Programming Language :: Python",
|
|
"Programming Language :: Python :: 3",
|
|
"Programming Language :: Python :: 3 :: Only",
|
|
"Intended Audience :: Developers",
|
|
"License :: OSI Approved :: GNU Lesser General Public License v3 (LGPLv3)",
|
|
"Operating System :: OS Independent",
|
|
"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
|
|
]
|
|
|
|
[project.optional-dependencies]
|
|
cli = [
|
|
"peakrdl-cli >= 1.2.3",
|
|
]
|
|
|
|
[project.urls]
|
|
Source = "https://github.com/SystemRDL/PeakRDL-regblock"
|
|
Tracker = "https://github.com/SystemRDL/PeakRDL-regblock/issues"
|
|
Changelog = "https://github.com/SystemRDL/PeakRDL-regblock/releases"
|
|
Documentation = "https://peakrdl-regblock.readthedocs.io/"
|
|
|
|
[tool.setuptools.dynamic]
|
|
version = {attr = "peakrdl_regblock.__about__.__version__"}
|
|
|
|
[project.entry-points."peakrdl.exporters"]
|
|
regblock = "peakrdl_regblock.__peakrdl__:Exporter"
|