49 lines
2.0 KiB
Systemverilog
49 lines
2.0 KiB
Systemverilog
{%- if cpuif.is_interface -%}
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`ifndef SYNTHESIS
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initial begin
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assert_bad_addr_width: assert($bits({{cpuif.signal("paddr")}}) >= {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH)
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else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("paddr")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH);
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assert_bad_data_width: assert($bits({{cpuif.signal("pwdata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
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else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("pwdata")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH);
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end
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`endif
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{% endif -%}
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// Request
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logic is_active;
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always_ff {{get_always_ff_event(cpuif.reset)}} begin
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if({{get_resetsignal(cpuif.reset)}}) begin
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is_active <= '0;
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cpuif_req <= '0;
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cpuif_req_is_wr <= '0;
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cpuif_addr <= '0;
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cpuif_wr_data <= '0;
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end else begin
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if(~is_active) begin
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if({{cpuif.signal("psel")}}) begin
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is_active <= '1;
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cpuif_req <= '1;
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cpuif_req_is_wr <= {{cpuif.signal("pwrite")}};
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{%- if cpuif.data_width_bytes == 1 %}
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cpuif_addr <= {{cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:0];
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{%- else %}
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cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
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{%- endif %}
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cpuif_wr_data <= {{cpuif.signal("pwdata")}};
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end
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end else begin
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cpuif_req <= '0;
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if(cpuif_rd_ack || cpuif_wr_ack) begin
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is_active <= '0;
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end
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end
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end
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end
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assign cpuif_wr_biten = '1;
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// Response
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assign {{cpuif.signal("pready")}} = cpuif_rd_ack | cpuif_wr_ack;
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assign {{cpuif.signal("prdata")}} = cpuif_rd_data;
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assign {{cpuif.signal("pslverr")}} = cpuif_rd_err | cpuif_wr_err;
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