95fda3abaa
* Initial plan * Refactor cpuif classes to use Interface abstraction Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix type annotation consistency in Interface.signal() Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add runtime validation and documentation for indexer types Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Remove unused variable in SVInterface.signal() Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix master port directions in APB3 and APB4 flat interfaces Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix AXI4LiteCpuifFlat and apply code formatting Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * PSELx -> PSEL * cleanup marker warnings --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
85 lines
3.6 KiB
Python
85 lines
3.6 KiB
Python
"""AXI4-Lite-specific interface implementations."""
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from systemrdl.node import AddressableNode
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from ..interface import FlatInterface, SVInterface
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class AXI4LiteSVInterface(SVInterface):
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"""AXI4-Lite SystemVerilog interface."""
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def get_interface_type(self) -> str:
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return "axi4lite_intf"
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def get_slave_name(self) -> str:
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return "s_axil"
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def get_master_prefix(self) -> str:
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return "m_axil_"
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class AXI4LiteFlatInterface(FlatInterface):
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"""AXI4-Lite flat signal interface."""
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def get_slave_prefix(self) -> str:
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return "s_axil_"
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def get_master_prefix(self) -> str:
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return "m_axil_"
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def _get_slave_port_declarations(self, slave_prefix: str) -> list[str]:
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return [
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# Write address channel
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f"input logic {slave_prefix}AWVALID",
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f"output logic {slave_prefix}AWREADY",
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f"input logic [{self.cpuif.addr_width - 1}:0] {slave_prefix}AWADDR",
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f"input logic [2:0] {slave_prefix}AWPROT",
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# Write data channel
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f"input logic {slave_prefix}WVALID",
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f"output logic {slave_prefix}WREADY",
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f"input logic [{self.cpuif.data_width - 1}:0] {slave_prefix}WDATA",
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f"input logic [{self.cpuif.data_width // 8 - 1}:0] {slave_prefix}WSTRB",
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# Write response channel
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f"output logic {slave_prefix}BVALID",
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f"input logic {slave_prefix}BREADY",
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f"output logic [1:0] {slave_prefix}BRESP",
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# Read address channel
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f"input logic {slave_prefix}ARVALID",
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f"output logic {slave_prefix}ARREADY",
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f"input logic [{self.cpuif.addr_width - 1}:0] {slave_prefix}ARADDR",
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f"input logic [2:0] {slave_prefix}ARPROT",
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# Read data channel
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f"output logic {slave_prefix}RVALID",
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f"input logic {slave_prefix}RREADY",
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f"output logic [{self.cpuif.data_width - 1}:0] {slave_prefix}RDATA",
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f"output logic [1:0] {slave_prefix}RRESP",
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]
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def _get_master_port_declarations(self, child: AddressableNode, master_prefix: str) -> list[str]:
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return [
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# Write address channel
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f"output logic {self.signal('AWVALID', child)}",
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f"input logic {self.signal('AWREADY', child)}",
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f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('AWADDR', child)}",
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f"output logic [2:0] {self.signal('AWPROT', child)}",
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# Write data channel
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f"output logic {self.signal('WVALID', child)}",
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f"input logic {self.signal('WREADY', child)}",
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f"output logic [{self.cpuif.data_width - 1}:0] {self.signal('WDATA', child)}",
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f"output logic [{self.cpuif.data_width // 8 - 1}:0] {self.signal('WSTRB', child)}",
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# Write response channel
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f"input logic {self.signal('BVALID', child)}",
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f"output logic {self.signal('BREADY', child)}",
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f"input logic [1:0] {self.signal('BRESP', child)}",
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# Read address channel
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f"output logic {self.signal('ARVALID', child)}",
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f"input logic {self.signal('ARREADY', child)}",
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f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('ARADDR', child)}",
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f"output logic [2:0] {self.signal('ARPROT', child)}",
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# Read data channel
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f"input logic {self.signal('RVALID', child)}",
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f"output logic {self.signal('RREADY', child)}",
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f"input logic [{self.cpuif.data_width - 1}:0] {self.signal('RDATA', child)}",
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f"input logic [1:0] {self.signal('RRESP', child)}",
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]
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