80 lines
2.8 KiB
Systemverilog
80 lines
2.8 KiB
Systemverilog
//==========================================================
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// Module: {{ds.module_name}}
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// Description: CPU Interface Bus Decoder
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// Author: PeakRDL-BusDecoder
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// License: LGPL-3.0
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// Date: {{current_date}}
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// Version: {{version}}
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// Links:
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// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
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//==========================================================
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module {{ds.module_name}}
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{%- if cpuif.parameters %} #(
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{{cpuif.parameters|join(",\n")|indent(4)}}
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) {%- endif %} (
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{{cpuif.port_declaration|indent(4)}}
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);
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//--------------------------------------------------------------------------
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// CPU Bus interface logic
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//--------------------------------------------------------------------------
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logic cpuif_req;
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logic cpuif_wr_en;
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logic cpuif_rd_en;
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logic [{{cpuif.addr_width-1}}:0] cpuif_wr_addr;
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logic [{{cpuif.addr_width-1}}:0] cpuif_rd_addr;
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logic cpuif_wr_ack;
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logic cpuif_wr_err;
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logic [{{cpuif.data_width-1}}:0] cpuif_wr_data;
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logic [{{cpuif.data_width//8-1}}:0] cpuif_wr_byte_en;
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logic cpuif_rd_ack;
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logic cpuif_rd_err;
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logic [{{cpuif.data_width-1}}:0] cpuif_rd_data;
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//--------------------------------------------------------------------------
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// Child instance signals
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//--------------------------------------------------------------------------
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{{cpuif_select|walk|indent(4)}}
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cpuif_sel_t cpuif_wr_sel;
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cpuif_sel_t cpuif_rd_sel;
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//--------------------------------------------------------------------------
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// Slave <-> Internal CPUIF <-> Master
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//--------------------------------------------------------------------------
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{{cpuif.get_implementation()|indent(4)}}
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//--------------------------------------------------------------------------
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// Write Address Decoder
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//--------------------------------------------------------------------------
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always_comb begin
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// Default all write select signals to 0
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cpuif_wr_sel = '0;
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if (cpuif_req && cpuif_wr_en) begin
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// A write request is pending
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{{cpuif_decode|walk(flavor=cpuif_decode_flavor.WRITE)|indent(12)}}
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end else begin
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// No write request, all select signals remain 0
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end
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end
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//--------------------------------------------------------------------------
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// Read Address Decoder
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//--------------------------------------------------------------------------
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always_comb begin
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// Default all read select signals to 0
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cpuif_rd_sel = '0;
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if (cpuif_req && cpuif_rd_en) begin
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// A read request is pending
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{{cpuif_decode|walk(flavor=cpuif_decode_flavor.READ)|indent(12)}}
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end else begin
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// No read request, all select signals remain 0
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end
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end
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endmodule
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{# (eof newline anchor) #}
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