126 lines
3.6 KiB
Python
126 lines
3.6 KiB
Python
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from collections.abc import Callable
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from systemrdl.node import AddrmapNode
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from peakrdl_busdecoder.design_state import DesignState
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class TestDesignState:
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"""Test the DesignState class."""
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def test_design_state_basic(self, compile_rdl:Callable[..., AddrmapNode])->None:
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"""Test basic DesignState initialization."""
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rdl_source = """
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addrmap test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {})
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assert ds.top_node == top
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assert ds.module_name == "test"
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assert ds.package_name == "test_pkg"
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assert ds.cpuif_data_width == 32 # Should infer from 32-bit field
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assert ds.addr_width > 0
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def test_design_state_custom_module_name(self, compile_rdl:Callable[..., AddrmapNode])->None:
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"""Test DesignState with custom module name."""
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rdl_source = """
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addrmap test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {"module_name": "custom_module"})
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assert ds.module_name == "custom_module"
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assert ds.package_name == "custom_module_pkg"
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def test_design_state_custom_package_name(self, compile_rdl:Callable[..., AddrmapNode])->None:
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"""Test DesignState with custom package name."""
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rdl_source = """
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addrmap test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {"package_name": "custom_pkg"})
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assert ds.package_name == "custom_pkg"
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def test_design_state_custom_address_width(self, compile_rdl:Callable[..., AddrmapNode])->None:
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"""Test DesignState with custom address width."""
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rdl_source = """
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addrmap test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {"address_width": 16})
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assert ds.addr_width == 16
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def test_design_state_unroll_arrays(self, compile_rdl:Callable[..., AddrmapNode])->None:
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"""Test DesignState with cpuif_unroll option."""
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rdl_source = """
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addrmap test {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_regs[4] @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {"cpuif_unroll": True})
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assert ds.cpuif_unroll is True
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def test_design_state_64bit_registers(self, compile_rdl:Callable[..., AddrmapNode])->None:
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"""Test DesignState with wider data width."""
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rdl_source = """
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addrmap test {
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reg {
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regwidth = 32;
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="test")
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ds = DesignState(top, {})
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# Should infer 32-bit data width from field
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assert ds.cpuif_data_width == 32
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