95fda3abaa
* Initial plan * Refactor cpuif classes to use Interface abstraction Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix type annotation consistency in Interface.signal() Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add runtime validation and documentation for indexer types Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Remove unused variable in SVInterface.signal() Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix master port directions in APB3 and APB4 flat interfaces Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix AXI4LiteCpuifFlat and apply code formatting Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * PSELx -> PSEL * cleanup marker warnings --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
57 lines
2.1 KiB
Python
57 lines
2.1 KiB
Python
"""APB3-specific interface implementations."""
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from systemrdl.node import AddressableNode
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from ..interface import FlatInterface, SVInterface
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class APB3SVInterface(SVInterface):
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"""APB3 SystemVerilog interface."""
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def get_interface_type(self) -> str:
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return "apb3_intf"
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def get_slave_name(self) -> str:
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return "s_apb"
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def get_master_prefix(self) -> str:
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return "m_apb_"
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class APB3FlatInterface(FlatInterface):
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"""APB3 flat signal interface."""
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def get_slave_prefix(self) -> str:
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return "s_apb_"
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def get_master_prefix(self) -> str:
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return "m_apb_"
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def _get_slave_port_declarations(self, slave_prefix: str) -> list[str]:
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return [
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f"input logic {slave_prefix}PCLK",
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f"input logic {slave_prefix}PRESETn",
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f"input logic {slave_prefix}PSEL",
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f"input logic {slave_prefix}PENABLE",
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f"input logic {slave_prefix}PWRITE",
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f"input logic [{self.cpuif.addr_width - 1}:0] {slave_prefix}PADDR",
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f"input logic [{self.cpuif.data_width - 1}:0] {slave_prefix}PWDATA",
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f"output logic [{self.cpuif.data_width - 1}:0] {slave_prefix}PRDATA",
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f"output logic {slave_prefix}PREADY",
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f"output logic {slave_prefix}PSLVERR",
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]
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def _get_master_port_declarations(self, child: AddressableNode, master_prefix: str) -> list[str]:
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return [
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f"output logic {self.signal('PCLK', child)}",
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f"output logic {self.signal('PRESETn', child)}",
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f"output logic {self.signal('PSEL', child)}",
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f"output logic {self.signal('PENABLE', child)}",
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f"output logic {self.signal('PWRITE', child)}",
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f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('PADDR', child)}",
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f"output logic [{self.cpuif.data_width - 1}:0] {self.signal('PWDATA', child)}",
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f"input logic [{self.cpuif.data_width - 1}:0] {self.signal('PRDATA', child)}",
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f"input logic {self.signal('PREADY', child)}",
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f"input logic {self.signal('PSLVERR', child)}",
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]
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