3d823572cc
* Initial plan * Fix nonconstant index error by using unpacked structs and arrays Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add comprehensive tests for Questa compatibility with instance arrays Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add intermediate signals for interface array fanin to fix Questa compatibility Questa simulator rejects indexing interface arrays with non-constant variables in procedural blocks (always_comb). This fix creates intermediate unpacked array signals that are assigned from interface arrays using generate loops (with genvar), then references those intermediates in the fanin logic. Changes: - Added fanin_intermediate_gen.py to generate intermediate signals - Modified APB3/APB4/AXI4-Lite cpuif classes to use intermediates for interface arrays - Updated templates to include intermediate signal section - Intermediate signals use genvar indexing (legal) instead of variable indexing (illegal in Questa) Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix type checking and formatting issues in fanin intermediate generator - Added proper null checks for node.array_dimensions to avoid type errors - Used getattr() to safely access is_interface and _interface attributes - Added early returns when interface is None to prevent errors - Fixed formatting issues in fanin_intermediate_gen.py - All type checks now pass (only pre-existing errors remain in other files) - All 67 tests still pass Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix test collection when cocotb is not installed The cocotb test files (test_runner.py) have imports that fail at module level when cocotb is not installed, causing pytest collection to fail. This prevents running tests in environments without cocotb dependencies. Solution: Updated conftest.py to conditionally ignore cocotb tests when cocotb is not available, allowing tests to pass in both environments (with and without cocotb). - When cocotb is available: only ignore test_register_access.py files (existing behavior) - When cocotb is not available: ignore all files under cocotb/** directories This allows CI to run all 67 non-simulation tests successfully without requiring cocotb/verilator dependencies for basic testing. Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * add default for unpacked struct * cocotb is test dependancy * Refactor fanin intermediate signal logic to cpuif level Moved the interface-specific signal assignment logic from fanin_intermediate_gen.py to individual cpuif classes (APB3Cpuif, APB4Cpuif, AXI4LiteCpuif). This follows better architecture principles where each cpuif knows which signals it needs. Changes: - Added fanin_intermediate_assignments() method to BaseCpuif - Implemented fanin_intermediate_assignments() in APB3Cpuif, APB4Cpuif, and AXI4LiteCpuif - Updated FaninIntermediateGenerator to call the cpuif method instead of checking interface type - Removed interface type checking logic from fanin_intermediate_gen.py This makes the code more maintainable and follows the single responsibility principle - each cpuif class knows its own signal requirements. Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
87 lines
3.3 KiB
Python
87 lines
3.3 KiB
Python
from typing import TYPE_CHECKING, overload
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from systemrdl.node import AddressableNode
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from ...utils import get_indexed_path
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from ..base_cpuif import BaseCpuif
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from .axi4_lite_interface import AXI4LiteFlatInterface
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if TYPE_CHECKING:
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from ...exporter import BusDecoderExporter
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class AXI4LiteCpuifFlat(BaseCpuif):
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"""Verilator-friendly variant that flattens the AXI4-Lite interface ports."""
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template_path = "axi4_lite_tmpl.sv"
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def __init__(self, exp: "BusDecoderExporter") -> None:
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super().__init__(exp)
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self._interface = AXI4LiteFlatInterface(self)
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@property
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def is_interface(self) -> bool:
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return self._interface.is_interface
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@property
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def port_declaration(self) -> str:
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"""Returns the port declaration for the AXI4-Lite interface."""
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return self._interface.get_port_declaration("s_axil_", "m_axil_")
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@overload
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def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
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@overload
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def signal(self, signal: str, node: AddressableNode, indexer: str | None = None) -> str: ...
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def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
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return self._interface.signal(signal, node, indexer)
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def fanout(self, node: AddressableNode) -> str:
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fanout: dict[str, str] = {}
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wr_sel = f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
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rd_sel = f"cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
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# Write address channel
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fanout[self.signal("AWVALID", node, "gi")] = wr_sel
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fanout[self.signal("AWADDR", node, "gi")] = self.signal("AWADDR")
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fanout[self.signal("AWPROT", node, "gi")] = self.signal("AWPROT")
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# Write data channel
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fanout[self.signal("WVALID", node, "gi")] = wr_sel
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fanout[self.signal("WDATA", node, "gi")] = "cpuif_wr_data"
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fanout[self.signal("WSTRB", node, "gi")] = "cpuif_wr_byte_en"
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# Write response channel (master -> slave)
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fanout[self.signal("BREADY", node, "gi")] = self.signal("BREADY")
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# Read address channel
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fanout[self.signal("ARVALID", node, "gi")] = rd_sel
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fanout[self.signal("ARADDR", node, "gi")] = self.signal("ARADDR")
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fanout[self.signal("ARPROT", node, "gi")] = self.signal("ARPROT")
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# Read data channel (master -> slave)
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fanout[self.signal("RREADY", node, "gi")] = self.signal("RREADY")
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return "\n".join(f"assign {lhs} = {rhs};" for lhs, rhs in fanout.items())
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def fanin(self, node: AddressableNode | None = None) -> str:
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fanin: dict[str, str] = {}
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if node is None:
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fanin["cpuif_rd_ack"] = "'0"
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fanin["cpuif_rd_err"] = "'0"
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else:
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# Read side: ack comes from RVALID; err if RRESP[1] is set (SLVERR/DECERR)
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fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
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fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
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return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
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def readback(self, node: AddressableNode | None = None) -> str:
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fanin: dict[str, str] = {}
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if node is None:
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fanin["cpuif_rd_data"] = "'0"
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else:
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fanin["cpuif_rd_data"] = self.signal("RDATA", node, "i")
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return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
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