233 lines
7.7 KiB
ReStructuredText
233 lines
7.7 KiB
ReStructuredText
.. _cpuif_protocol:
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Internal CPUIF Protocol
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=======================
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Internally, the busdecoder generator uses a common CPU interface handshake
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protocol. This strobe-based protocol is designed to add minimal overhead to the
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busdecoder implementation, while also being flexible enough to support advanced
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features of a variety of bus interface standards.
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Signal Descriptions
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-------------------
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Request
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^^^^^^^
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cpuif_req
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When asserted, a read or write transfer will be initiated.
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Denotes that the following signals are valid: ``cpuif_addr``,
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``cpuif_req_is_wr``, and ``cpuif_wr_data``.
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A transfer will only initiate if the relevant stall signal is not asserted.
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If stalled, the request shall be held until accepted. A request's parameters
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(type, address, etc) shall remain static throughout the stall.
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cpuif_addr
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Byte-address of the transfer.
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cpuif_req_is_wr
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If ``1``, denotes that the current transfer is a write. Otherwise transfer is
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a read.
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cpuif_wr_data
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Data to be written for the write transfer. This signal is ignored for read
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transfers.
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cpuif_wr_biten
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Active-high bit-level write-enable strobes.
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Only asserted bit positions will change the register value during a write
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transfer.
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cpuif_req_stall_rd
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If asserted, and the next pending request is a read operation, then the
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transfer will not be accepted until this signal is deasserted.
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cpuif_req_stall_wr
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If asserted, and the next pending request is a write operation, then the
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transfer will not be accepted until this signal is deasserted.
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Read Response
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^^^^^^^^^^^^^
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cpuif_rd_ack
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Single-cycle strobe indicating a read transfer has completed.
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Qualifies that the following signals are valid: ``cpuif_rd_err`` and
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``cpuif_rd_data``
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cpuif_rd_err
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If set, indicates that the read transaction failed and the CPUIF logic
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should return an error response if possible.
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cpuif_rd_data
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Read data. Is sampled on the same cycle that ``cpuif_rd_ack`` is asserted.
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Write Response
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^^^^^^^^^^^^^^
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cpuif_wr_ack
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Single-cycle strobe indicating a write transfer has completed.
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Qualifies that the ``cpuif_wr_err`` signal is valid.
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cpuif_wr_err
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If set, indicates that the write transaction failed and the CPUIF logic
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should return an error response if possible.
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Transfers
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---------
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Transfers have the following characteristics:
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* Only one transfer can be initiated per clock-cycle. This is implicit as there
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is only one set of request signals.
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* The register block implementation shall guarantee that only one response can be
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asserted in a given clock cycle. Only one ``cpuif_*_ack`` signal can be
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asserted at a time.
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* Responses shall arrive in the same order as their corresponding request was
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dispatched.
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Basic Transfer
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^^^^^^^^^^^^^^
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Depending on the configuration of the exported register block, transfers can be
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fully combinational or they may require one or more clock cycles to complete.
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Both are valid and CPU interface logic shall be designed to anticipate either.
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.. wavedrom::
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{
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"signal": [
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{"name": "clk", "wave": "p...."},
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{"name": "cpuif_req", "wave": "010.."},
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{"name": "cpuif_req_is_wr", "wave": "x2x.."},
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{"name": "cpuif_addr", "wave": "x2x..", "data": ["A"]},
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{},
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{"name": "cpuif_*_ack", "wave": "010.."},
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{"name": "cpuif_*_err", "wave": "x2x.."}
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],
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"foot": {
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"text": "Zero-latency transfer"
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}
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}
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.. wavedrom::
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{
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"signal": [
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{"name": "clk", "wave": "p..|..."},
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{"name": "cpuif_req", "wave": "010|..."},
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{"name": "cpuif_req_is_wr", "wave": "x2x|..."},
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{"name": "cpuif_addr", "wave": "x2x|...", "data": ["A"]},
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{},
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{"name": "cpuif_*_ack", "wave": "0..|10."},
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{"name": "cpuif_*_err", "wave": "x..|2x."}
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],
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"foot": {
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"text": "Transfer with non-zero latency"
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}
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}
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Read & Write Transactions
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-------------------------
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Waveforms below show the timing relationship of simple read/write transactions.
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For brevity, only showing non-zero latency transfers.
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.. wavedrom::
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{
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"signal": [
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{"name": "clk", "wave": "p..|..."},
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{"name": "cpuif_req", "wave": "010|..."},
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{"name": "cpuif_req_is_wr", "wave": "x0x|..."},
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{"name": "cpuif_addr", "wave": "x3x|...", "data": ["A"]},
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{},
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{"name": "cpuif_rd_ack", "wave": "0..|10."},
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{"name": "cpuif_rd_err", "wave": "x..|0x."},
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{"name": "cpuif_rd_data", "wave": "x..|5x.", "data": ["D"]}
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],
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"foot": {
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"text": "Read Transaction"
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}
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}
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.. wavedrom::
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{
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"signal": [
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{"name": "clk", "wave": "p..|..."},
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{"name": "cpuif_req", "wave": "010|..."},
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{"name": "cpuif_req_is_wr", "wave": "x1x|..."},
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{"name": "cpuif_addr", "wave": "x3x|...", "data": ["A"]},
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{"name": "cpuif_wr_data", "wave": "x5x|...", "data": ["D"]},
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{},
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{"name": "cpuif_wr_ack", "wave": "0..|10."},
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{"name": "cpuif_wr_err", "wave": "x..|0x."}
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],
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"foot": {
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"text": "Write Transaction"
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}
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}
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Transaction Pipelining & Stalls
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-------------------------------
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If the CPU interface supports it, read and write operations can be pipelined.
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.. wavedrom::
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{
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"signal": [
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{"name": "clk", "wave": "p......"},
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{"name": "cpuif_req", "wave": "01..0.."},
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{"name": "cpuif_req_is_wr", "wave": "x0..x.."},
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{"name": "cpuif_addr", "wave": "x333x..", "data": ["A1", "A2", "A3"]},
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{},
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{"name": "cpuif_rd_ack", "wave": "0.1..0."},
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{"name": "cpuif_rd_err", "wave": "x.0..x."},
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{"name": "cpuif_rd_data", "wave": "x.555x.", "data": ["D1", "D2", "D3"]}
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]
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}
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It is very likely that the transfer latency of a read transaction will not
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be the same as a write for a given register block configuration. Typically read
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operations will be more deeply pipelined. This latency asymmetry would create a
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hazard for response collisions.
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In order to eliminate this hazard, additional stall signals (``cpuif_req_stall_rd``
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and ``cpuif_req_stall_wr``) are provided to delay the next incoming transfer
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request if necessary. When asserted, the CPU interface shall hold the next pending
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request until the stall is cleared.
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For non-pipelined CPU interfaces that only allow one outstanding transaction at a time,
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these stall signals can be safely ignored.
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In the following example, the busdecoder is configured such that:
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* A read transaction takes 1 clock cycle to complete
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* A write transaction takes 0 clock cycles to complete
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.. wavedrom::
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{
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"signal": [
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{"name": "clk", "wave": "p......."},
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{"name": "cpuif_req", "wave": "01.....0"},
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{"name": "cpuif_req_is_wr", "wave": "x1.0.1.x"},
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{"name": "cpuif_addr", "wave": "x33443.x", "data": ["W1", "W2", "R1", "R2", "W3"]},
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{"name": "cpuif_req_stall_wr", "wave": "0...1.0."},
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{},
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{"name": "cpuif_rd_ack", "wave": "0...220.", "data": ["R1", "R2"]},
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{"name": "cpuif_wr_ack", "wave": "0220..20", "data": ["W1", "W2", "W3"]}
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]
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}
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In the above waveform, observe that:
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* The ``R2`` read request is not affected by the assertion of the write stall,
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since the write stall only applies to write requests.
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* The ``W3`` write request is stalled for one cycle, and is accepted once the stall is cleared.
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