37 lines
1.5 KiB
ReStructuredText
37 lines
1.5 KiB
ReStructuredText
Introduction
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============
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The CPU interface logic layer provides an abstraction between the
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application-specific bus protocol and the internal register file logic.
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When exporting a design, you can select from a variety of popular CPU interface
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protocols. These are described in more detail in the pages that follow.
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Bus Width
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^^^^^^^^^
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The CPU interface bus width is automatically determined from the contents of the
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design being exported. The bus width is equal to the widest ``accesswidth``
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encountered in the design.
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Addressing
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^^^^^^^^^^
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The busdecoder exporter will always generate its address decoding logic using local
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address offsets. The absolute address offset of your device shall be
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handled by your system interconnect, and present addresses to the busdecoder that
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only include the local offset.
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For example, consider a fictional AXI4-Lite device that:
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- Consumes 4 kB of address space (``0x000``-``0xFFF``).
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- The device is instantiated in your system at global address range ``0x30_0000 - 0x50_0FFF``.
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- After decoding transactions destined to the device, the system interconnect shall
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ensure that AxADDR values are presented to the device as relative addresses - within
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the range of ``0x000``-``0xFFF``.
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- If care is taken to align the global address offset to the size of the device,
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creating a relative address is as simple as pruning down address bits.
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By default, the bit-width of the address bus will be the minimum size to span the contents
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of the register block. If needed, the address width can be overridden to a larger range.
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