Files
PeakRDL-BusDecoder/pyproject.toml
2025-10-10 22:30:59 -07:00

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1.6 KiB
TOML

[build-system]
requires = ["setuptools", "setuptools-scm"]
build-backend = "setuptools.build_meta"
[project]
name = "peakrdl-busdecoder"
dynamic = ["version"]
requires-python = ">=3.7"
dependencies = ["systemrdl-compiler ~= 1.29", "Jinja2>=2.11"]
authors = [{ name = "Alex Mykyta" }]
description = "Compile SystemRDL into a SystemVerilog control/status register (CSR) block"
readme = "README.md"
license = { text = "LGPLv3" }
keywords = [
"SystemRDL",
"PeakRDL",
"CSR",
"compiler",
"tool",
"registers",
"generator",
"Verilog",
"SystemVerilog",
"register abstraction layer",
"FPGA",
"ASIC",
]
classifiers = [
"Development Status :: 5 - Production/Stable",
"Programming Language :: Python",
"Programming Language :: Python :: 3",
"Programming Language :: Python :: 3 :: Only",
"Intended Audience :: Developers",
"License :: OSI Approved :: GNU Lesser General Public License v3 (LGPLv3)",
"Operating System :: OS Independent",
"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
]
[project.optional-dependencies]
cli = ["peakrdl-cli >= 1.2.3"]
[project.urls]
Source = "https://github.com/SystemRDL/PeakRDL-busdecoder"
Tracker = "https://github.com/SystemRDL/PeakRDL-busdecoder/issues"
Changelog = "https://github.com/SystemRDL/PeakRDL-busdecoder/releases"
Documentation = "https://peakrdl-busdecoder.readthedocs.io/"
[tool.setuptools.dynamic]
version = { attr = "peakrdl_busdecoder.__about__.__version__" }
[project.entry-points."peakrdl.exporters"]
busdecoder = "peakrdl_busdecoder.__peakrdl__:Exporter"