80 lines
1.7 KiB
Systemverilog
80 lines
1.7 KiB
Systemverilog
module external_reg #(
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parameter WIDTH = 32,
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parameter SUBWORDS = 1
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)(
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input wire clk,
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input wire rst,
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input wire [SUBWORDS-1:0] req,
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input wire req_is_wr,
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input wire [WIDTH-1:0] wr_data,
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input wire [WIDTH-1:0] wr_biten,
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output logic rd_ack,
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output logic [WIDTH-1:0] rd_data,
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output logic wr_ack
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);
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timeunit 1ps;
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timeprecision 1ps;
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logic [SUBWORDS-1:0][WIDTH-1:0] value;
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task do_write(logic [SUBWORDS-1:0] strb, logic [WIDTH-1:0] data, logic [WIDTH-1:0] biten);
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automatic int delay;
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// Random delay
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delay = $urandom_range(3,0);
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repeat(delay) @(posedge clk)
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$info("Write delay: %d", delay);
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for(int i=0; i<SUBWORDS; i++) begin
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if(strb[i]) begin
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for(int b=0; b<WIDTH; b++) begin
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if(biten[b]) value[i][b] <= data[b];
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end
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end
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end
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wr_ack <= '1;
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endtask
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task do_read(logic [SUBWORDS-1:0] strb);
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automatic int delay;
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// Random delay
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delay = $urandom_range(3,0);
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repeat(delay) @(posedge clk)
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$info("Read delay: %d", delay);
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for(int i=0; i<SUBWORDS; i++) begin
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if(strb[i]) begin
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rd_data <= value[i];
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end
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end
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rd_ack <= '1;
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endtask;
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initial begin
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rd_ack <= '0;
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rd_data <= '0;
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wr_ack <= '0;
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value <= '0;
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forever begin
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// Wait for next clock edge
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@(posedge clk);
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rd_ack <= '0;
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rd_data <= '0;
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wr_ack <= '0;
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// wait slightly longer to "peek" at the current cycle's state
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#1ns;
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if(!rst && req) begin
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$info("got request");
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if(req_is_wr) do_write(req, wr_data, wr_biten);
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else do_read(req);
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end
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end
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end
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endmodule
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