129 lines
3.7 KiB
Systemverilog
129 lines
3.7 KiB
Systemverilog
{% sv_line_anchor %}
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module tb;
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timeunit 10ps;
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timeprecision 1ps;
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class bitswap_cls #(W=1);
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static function logic [W-1:0] bitswap(logic [W-1:0] x);
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logic [W-1:0] result;
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result = {<<{x}};
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return result;
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endfunction
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endclass
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`define bitswap(x) (bitswap_cls#($bits(x))::bitswap(x))
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logic rst = '1;
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logic clk = '0;
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initial forever begin
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#5ns;
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clk = ~clk;
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end
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logic rst_n, arst, arst_n;
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assign rst_n = ~rst;
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assign arst = rst;
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assign arst_n = ~rst;
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//--------------------------------------------------------------------------
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// DUT Signal declarations
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//--------------------------------------------------------------------------
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{%- if exporter.hwif.has_input_struct %}
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busdecoder_pkg::busdecoder__in_t hwif_in;
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{%- endif %}
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{%- if exporter.hwif.has_output_struct %}
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busdecoder_pkg::busdecoder__out_t hwif_out;
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{%- endif %}
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{%- if exporter.ds.has_paritycheck %}
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logic parity_error;
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{%- endif %}
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{%- block declarations %}
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{%- endblock %}
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//--------------------------------------------------------------------------
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// Clocking
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//--------------------------------------------------------------------------
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default clocking cb @(posedge clk);
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default input #1step output #1;
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output rst;
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{%- if exporter.hwif.has_input_struct and testcase.clocking_hwif_in %}
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output hwif_in;
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{%- endif %}
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{%- if exporter.hwif.has_output_struct and testcase.clocking_hwif_out %}
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input hwif_out;
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{%- endif %}
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{%- if exporter.ds.has_paritycheck %}
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input parity_error;
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{%- endif %}
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{%- filter indent %}
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{%- block clocking_dirs %}
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{%- endblock %}
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{%- endfilter %}
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endclocking
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//--------------------------------------------------------------------------
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// CPUIF
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//--------------------------------------------------------------------------
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{{testcase.cpuif.get_tb_inst(testcase, exporter)|indent}}
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//--------------------------------------------------------------------------
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// DUT
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//--------------------------------------------------------------------------
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{% sv_line_anchor %}
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busdecoder dut (.*);
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{%- if exporter.hwif.has_output_struct %}
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{% sv_line_anchor %}
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initial begin
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logic [$bits(hwif_out)-1:0] tmp;
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forever begin
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##1;
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tmp = {>>{hwif_out}}; // Workaround for Xilinx's xsim - assign to tmp variable
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if(!rst) assert(!$isunknown(tmp)) else $error("hwif_out has X's!");
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{%- if exporter.ds.has_paritycheck %}
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if(!rst) assert(!$isunknown(parity_error)) else $error("parity_error has X's!");
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{%- endif %}
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end
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end
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{%- endif %}
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{% sv_line_anchor %}
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{%- block dut_support %}
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{%- endblock %}
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//--------------------------------------------------------------------------
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// Test Sequence
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//--------------------------------------------------------------------------
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initial begin
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cb.rst <= '1;
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{%- if exporter.hwif.has_input_struct and testcase.init_hwif_in %}
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cb.hwif_in <= '{default: '0};
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{%- endif %}
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begin
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{%- filter indent(8) %}
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{%- block seq %}
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{%- endblock %}
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{%- endfilter %}
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end
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{% sv_line_anchor %}
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##5;
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$finish();
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end
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//--------------------------------------------------------------------------
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// Monitor for timeout
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//--------------------------------------------------------------------------
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initial begin
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##{{testcase.timeout_clk_cycles}};
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$fatal(1, "Test timed out after {{testcase.timeout_clk_cycles}} clock cycles");
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end
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endmodule
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