312 lines
8.6 KiB
Systemverilog
312 lines
8.6 KiB
Systemverilog
{% extends "lib/tb_base.sv" %}
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{%- block dut_support %}
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{% sv_line_anchor %}
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external_reg ext_reg_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.ext_reg.req),
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.req_is_wr(hwif_out.ext_reg.req_is_wr),
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.wr_data(hwif_out.ext_reg.wr_data),
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.wr_biten(hwif_out.ext_reg.wr_biten),
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.rd_ack(hwif_in.ext_reg.rd_ack),
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.rd_data(hwif_in.ext_reg.rd_data),
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.wr_ack(hwif_in.ext_reg.wr_ack)
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);
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external_reg #(
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.SUBWORDS(2)
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) wide_ext_reg_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.wide_ext_reg.req),
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.req_is_wr(hwif_out.wide_ext_reg.req_is_wr),
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.wr_data(hwif_out.wide_ext_reg.wr_data),
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.wr_biten(hwif_out.wide_ext_reg.wr_biten),
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.rd_ack(hwif_in.wide_ext_reg.rd_ack),
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.rd_data(hwif_in.wide_ext_reg.rd_data),
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.wr_ack(hwif_in.wide_ext_reg.wr_ack)
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);
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for(genvar i=0; i<32; i++) begin : array
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external_reg ext_reg_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.ext_reg_array[i].req),
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.req_is_wr(hwif_out.ext_reg_array[i].req_is_wr),
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.wr_data(hwif_out.ext_reg_array[i].wr_data),
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.wr_biten(hwif_out.ext_reg_array[i].wr_biten),
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.rd_ack(hwif_in.ext_reg_array[i].rd_ack),
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.rd_data(hwif_in.ext_reg_array[i].rd_data),
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.wr_ack(hwif_in.ext_reg_array[i].wr_ack)
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);
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end
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external_block #(
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.ADDR_WIDTH(5)
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) rf_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.rf.req),
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.req_is_wr(hwif_out.rf.req_is_wr),
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.addr(hwif_out.rf.addr),
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.wr_data(hwif_out.rf.wr_data),
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.wr_biten(hwif_out.rf.wr_biten),
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.rd_ack(hwif_in.rf.rd_ack),
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.rd_data(hwif_in.rf.rd_data),
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.wr_ack(hwif_in.rf.wr_ack)
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);
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external_block #(
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.ADDR_WIDTH(5)
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) am_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.am.req),
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.req_is_wr(hwif_out.am.req_is_wr),
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.addr(hwif_out.am.addr),
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.wr_data(hwif_out.am.wr_data),
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.wr_biten(hwif_out.am.wr_biten),
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.rd_ack(hwif_in.am.rd_ack),
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.rd_data(hwif_in.am.rd_data),
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.wr_ack(hwif_in.am.wr_ack)
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);
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external_block #(
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.ADDR_WIDTH(5)
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) mm_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.mm.req),
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.req_is_wr(hwif_out.mm.req_is_wr),
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.addr(hwif_out.mm.addr),
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.wr_data(hwif_out.mm.wr_data),
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.wr_biten(hwif_out.mm.wr_biten),
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.rd_ack(hwif_in.mm.rd_ack),
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.rd_data(hwif_in.mm.rd_data),
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.wr_ack(hwif_in.mm.wr_ack)
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);
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external_reg wo_reg_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.wo_reg.req),
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.req_is_wr(hwif_out.wo_reg.req_is_wr),
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.wr_data(hwif_out.wo_reg.wr_data),
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.wr_biten(hwif_out.wo_reg.wr_biten),
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.rd_ack(),
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.rd_data(),
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.wr_ack(hwif_in.wo_reg.wr_ack)
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);
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external_reg ro_reg_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.ro_reg.req),
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.req_is_wr(hwif_out.ro_reg.req_is_wr),
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.wr_data(32'b0),
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.wr_biten(32'b0),
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.rd_ack(hwif_in.ro_reg.rd_ack),
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.rd_data(hwif_in.ro_reg.rd_data),
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.wr_ack()
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);
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external_reg #(
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.SUBWORDS(2)
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) wide_wo_reg_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.wide_wo_reg.req),
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.req_is_wr(hwif_out.wide_wo_reg.req_is_wr),
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.wr_data(hwif_out.wide_wo_reg.wr_data),
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.wr_biten(hwif_out.wide_wo_reg.wr_biten),
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.rd_ack(),
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.rd_data(),
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.wr_ack(hwif_in.wide_wo_reg.wr_ack)
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);
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external_reg #(
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.SUBWORDS(2)
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) wide_ro_reg_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.wide_ro_reg.req),
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.req_is_wr(hwif_out.wide_ro_reg.req_is_wr),
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.wr_data(32'b0),
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.wr_biten(32'b0),
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.rd_ack(hwif_in.wide_ro_reg.rd_ack),
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.rd_data(hwif_in.wide_ro_reg.rd_data),
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.wr_ack()
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);
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{%- endblock %}
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{% block seq %}
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logic [31:0] x;
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{% sv_line_anchor %}
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##1;
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cb.rst <= '0;
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##1;
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//--------------------------------------------------------------------------
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// Simple read/write tests
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//--------------------------------------------------------------------------
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repeat(20) begin
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x = $urandom();
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cpuif.write('h00, x);
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cpuif.assert_read('h00, x);
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assert(ext_reg_inst.value == x);
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end
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for(int i=0; i<2; i++) begin
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repeat(20) begin
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x = $urandom();
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cpuif.write('h10 + i*4, x);
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cpuif.assert_read('h10 + i*4, x);
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assert(wide_ext_reg_inst.value[i] == x);
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end
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end
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for(int i=0; i<32; i++) begin
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repeat(20) begin
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x = $urandom();
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cpuif.write('h100 + i*4, x);
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cpuif.assert_read('h100 + i*4, x);
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end
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end
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for(int i=0; i<8; i++) begin
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repeat(20) begin
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x = $urandom();
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cpuif.write('h1000 + i*4, x);
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cpuif.assert_read('h1000 + i*4, x);
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assert(rf_inst.mem[i] == x);
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end
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end
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for(int i=0; i<8; i++) begin
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repeat(20) begin
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x = $urandom();
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cpuif.write('h2000 + i*4, x);
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cpuif.assert_read('h2000 + i*4, x);
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assert(am_inst.mem[i] == x);
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end
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end
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for(int i=0; i<8; i++) begin
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repeat(20) begin
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x = $urandom();
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cpuif.write('h3000 + i*4, x);
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cpuif.assert_read('h3000 + i*4, x);
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assert(mm_inst.mem[i] == x);
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end
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end
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repeat(20) begin
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x = $urandom();
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ro_reg_inst.value <= x;
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cpuif.write('h4000, ~x);
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cpuif.assert_read('h4000, x);
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assert(ro_reg_inst.value == x);
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end
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repeat(20) begin
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x = $urandom();
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cpuif.write('h4004, x);
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cpuif.assert_read('h4004, 0);
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assert(wo_reg_inst.value == x);
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end
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for(int i=0; i<2; i++) begin
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repeat(20) begin
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x = $urandom();
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wide_ro_reg_inst.value[i] <= x;
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cpuif.write('h4010 + i*4, ~x);
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cpuif.assert_read('h4010 + i*4, x);
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assert(wide_ro_reg_inst.value[i] == x);
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end
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end
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for(int i=0; i<2; i++) begin
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repeat(20) begin
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x = $urandom();
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cpuif.write('h4018 + i*4, x);
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cpuif.assert_read('h4018 + i*4, 0);
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assert(wide_wo_reg_inst.value[i] == x);
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end
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end
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//--------------------------------------------------------------------------
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// Pipelined access
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//--------------------------------------------------------------------------
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// init array with unique known value
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cpuif.write('h4, 'h1234);
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for(int i=0; i<32; i++) begin
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cpuif.write('h100 + i*4, 'h100 + i);
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end
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for(int i=0; i<8; i++) begin
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cpuif.write('h1000 + i*4, 'h1000 + i);
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cpuif.write('h2000 + i*4, 'h2000 + i);
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cpuif.write('h3000 + i*4, 'h3000 + i);
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end
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// random pipelined read/writes
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repeat(256) begin
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fork
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begin
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automatic int i, j;
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i = $urandom_range(31, 0);
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j = $urandom_range(7, 0);
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case($urandom_range(9,0))
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// external reg
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0: cpuif.write('h100 + i*4, 'h100 + i);
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1: cpuif.assert_read('h100 + i*4, 'h100 + i);
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// internal reg
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2: cpuif.write('h4, 'h1234);
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3: cpuif.assert_read('h4, 'h1234);
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// external regfile
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4: cpuif.write('h1000 + j*4, 'h1000 + j);
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5: cpuif.assert_read('h1000 + j*4, 'h1000 + j);
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// external addrmap
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6: cpuif.write('h2000 + j*4, 'h2000 + j);
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7: cpuif.assert_read('h2000 + j*4, 'h2000 + j);
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// external mem
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8: cpuif.write('h3000 + j*4, 'h3000 + j);
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9: cpuif.assert_read('h3000 + j*4, 'h3000 + j);
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endcase
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end
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join_none
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end
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wait fork;
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// Check register struct bit-order
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repeat(32) begin
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busdecoder_pkg::top__my_reg_alt__external__fields__in_t fields_in;
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busdecoder_pkg::top__my_reg_alt__external__fields__out_t fields_out;
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fields_in = $urandom();
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fields_out = $urandom();
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assert(fields_in.whatever_a == fields_in[3:2]);
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assert(fields_in.whatever_c == fields_in[15:8]);
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assert(fields_out.whatever_b == fields_out[4]);
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assert(fields_out.whatever_c == fields_out[15:8]);
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end
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{% endblock %}
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