13 lines
226 B
Systemverilog
13 lines
226 B
Systemverilog
{% extends "lib/tb_base.sv" %}
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{% block seq %}
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{% sv_line_anchor %}
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##1;
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cb.rst <= '0;
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##1;
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// check block size
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assert(busdecoder_pkg::REGBLOCK_SIZE == {{exporter.ds.top_node.size}});
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{% endblock %}
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