107 lines
2.4 KiB
Plaintext
107 lines
2.4 KiB
Plaintext
addrmap top {
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default regwidth = 16;
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default accesswidth = 16;
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default sw=rw;
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default hw=r;
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//--------------------------------------------------------------------------
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// Wide registers
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//--------------------------------------------------------------------------
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reg {
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regwidth = 64;
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buffer_writes = true;
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field {} f1[63:0] = 0;
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} reg1;
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reg {
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regwidth = 64;
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buffer_writes = true;
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field {} f1[0:63] = 0;
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} reg1_msb0;
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reg {
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regwidth = 32;
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buffer_writes = true;
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field {} f1[19:8] = 0;
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field {} f2[23:20] = 0;
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} reg2;
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reg {
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regwidth = 32;
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buffer_writes = true;
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field {} f1[8:19] = 0;
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field {} f2[20:23] = 0;
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} reg2_msb0;
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//--------------------------------------------------------------------------
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// Alternate Triggers
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//--------------------------------------------------------------------------
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reg myreg {
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buffer_writes;
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field {} f1[15:0] = 0;
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};
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// Trigger via another register
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myreg g1_r1;
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myreg g1_r2;
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g1_r1->buffer_writes = false;
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g1_r2->wbuffer_trigger = g1_r1;
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// triger from signal
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signal {
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activehigh;
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} trigger_sig;
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signal {
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activelow;
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} trigger_sig_n;
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myreg g2_r1;
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myreg g2_r2;
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g2_r1->wbuffer_trigger = trigger_sig;
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g2_r2->wbuffer_trigger = trigger_sig_n;
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// trigger from field
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myreg g3_r1;
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reg {
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field {
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sw=w; hw=r; singlepulse;
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} trig = 0;
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} g3_trig;
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g3_r1->wbuffer_trigger = g3_trig.trig;
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// trigger from propref
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myreg g4_r1;
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reg {
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field {
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hw=na;
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} trig_vec[3:0] = 0;
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} g4_trig;
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g4_r1->wbuffer_trigger = g4_trig.trig_vec->anded;
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//--------------------------------------------------------------------------
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// swmod behavior
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//--------------------------------------------------------------------------
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myreg g5_r1;
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g5_r1->wbuffer_trigger = trigger_sig;
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reg {
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field{
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sw=rw;
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hw=na;
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counter;
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} c[3:0] = 0;
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} g5_modcount;
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g5_modcount.c->incr = g5_r1.f1->swmod;
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myreg g6_r1;
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g6_r1.f1->rclr;
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g6_r1->wbuffer_trigger = trigger_sig;
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reg {
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field{
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sw=rw;
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hw=na;
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counter;
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} c[3:0] = 0;
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} g6_modcount;
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g6_modcount.c->incr = g6_r1.f1->swmod;
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};
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