21 lines
825 B
Systemverilog
21 lines
825 B
Systemverilog
//==========================================================
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// Package: {{ds.package_name}}
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// Description: CPU Interface Bus Decoder Package
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// Author: PeakRDL-BusDecoder
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// License: LGPL-3.0
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// Version: {{version}}
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// Links:
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// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
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//==========================================================
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package {{ds.package_name}};
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localparam {{ds.module_name.upper()}}_DATA_WIDTH = {{ds.cpuif_data_width}};
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localparam {{ds.module_name.upper()}}_MIN_ADDR_WIDTH = {{ds.addr_width}};
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localparam {{ds.module_name.upper()}}_SIZE = {{SVInt(ds.top_node.size)}};
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{%- for child in cpuif.addressable_children %}
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localparam {{ds.module_name.upper()}}_{{child.inst_name.upper()}}_ADDR_WIDTH = {{child.size|clog2}};
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{%- endfor %}
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endpackage
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{# (eof newline anchor) #}
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