251 lines
8.0 KiB
Python
251 lines
8.0 KiB
Python
"""Test handling of external nested addressable components."""
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from collections.abc import Callable
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from pathlib import Path
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from tempfile import TemporaryDirectory
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from systemrdl.node import AddrmapNode
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from peakrdl_busdecoder import BusDecoderExporter
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from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
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def test_external_nested_components_generate_correct_decoder(external_nested_rdl: AddrmapNode) -> None:
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"""Test that external nested components generate correct decoder logic.
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The decoder should:
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- Generate select signals for multicast and port[16]
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- NOT generate select signals for multicast.common[] or multicast.response
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- NOT generate invalid paths like multicast.common[i0]
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"""
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with TemporaryDirectory() as tmpdir:
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exporter = BusDecoderExporter()
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exporter.export(
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external_nested_rdl,
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tmpdir,
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cpuif_cls=APB4Cpuif,
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)
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# Read the generated module
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module_file = Path(tmpdir) / "buffer_t.sv"
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content = module_file.read_text()
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# Should have correct select signals
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assert "cpuif_wr_sel.multicast = 1'b1;" in content
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assert "cpuif_wr_sel.port[i0] = 1'b1;" in content
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# Should NOT have invalid nested paths
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assert "cpuif_wr_sel.multicast.common" not in content
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assert "cpuif_wr_sel.multicast.response" not in content
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assert "cpuif_rd_sel.multicast.common" not in content
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assert "cpuif_rd_sel.multicast.response" not in content
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# Verify struct is flat (no nested structs for external children)
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assert "typedef struct" in content
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assert "logic multicast;" in content
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assert "logic port[16];" in content
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def test_external_nested_components_generate_correct_interfaces(external_nested_rdl: AddrmapNode) -> None:
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"""Test that external nested components generate correct interface ports.
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The module should have:
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- One master interface for multicast
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- Array of 16 master interfaces for port[]
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- NO interfaces for internal components like common[] or response
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"""
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with TemporaryDirectory() as tmpdir:
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exporter = BusDecoderExporter()
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exporter.export(
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external_nested_rdl,
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tmpdir,
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cpuif_cls=APB4Cpuif,
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)
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# Read the generated module
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module_file = Path(tmpdir) / "buffer_t.sv"
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content = module_file.read_text()
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# Should have master interfaces for top-level external children
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assert "m_apb_multicast" in content
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assert "m_apb_port [16]" in content or "m_apb_port[16]" in content
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# Should NOT have interfaces for nested external children
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assert "m_apb_multicast_common" not in content
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assert "m_apb_multicast_response" not in content
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assert "m_apb_common" not in content
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assert "m_apb_response" not in content
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def test_non_external_nested_components_are_descended(compile_rdl: Callable[..., AddrmapNode]) -> None:
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"""Test that non-external nested components are still descended into.
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This is a regression test to ensure we didn't break normal nested
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component handling.
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"""
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rdl_source = """
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addrmap inner_block {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} inner_reg @ 0x0;
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};
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addrmap outer_block {
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inner_block inner @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="outer_block")
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with TemporaryDirectory() as tmpdir:
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exporter = BusDecoderExporter()
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# Use depth=0 to descend all the way down to registers
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exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif, max_decode_depth=0)
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# Read the generated module
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module_file = Path(tmpdir) / "outer_block.sv"
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content = module_file.read_text()
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# Should descend into inner and reference inner_reg
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assert "inner" in content
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assert "inner_reg" in content
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def test_max_decode_depth_parameter_exists(compile_rdl: Callable[..., AddrmapNode]) -> None:
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"""Test that max_decode_depth parameter can be set."""
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rdl_source = """
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addrmap simple {
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reg {
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field { sw=rw; hw=r; } data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="simple")
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with TemporaryDirectory() as tmpdir:
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exporter = BusDecoderExporter()
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# Should not raise an exception
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exporter.export(
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top,
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tmpdir,
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cpuif_cls=APB4Cpuif,
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max_decode_depth=2,
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)
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# Verify output was generated
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module_file = Path(tmpdir) / "simple.sv"
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assert module_file.exists()
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def test_unaligned_external_component_supported(compile_rdl: Callable[..., AddrmapNode]) -> None:
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"""Test that external components can be at unaligned addresses.
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This test verifies that external components don't need to be aligned
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to a power-of-2 multiple of their size, as the busdecoder supports
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unaligned access.
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"""
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rdl_source = """
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mem queue_t {
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name = "Queue";
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mementries = 1024;
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memwidth = 64;
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};
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addrmap buffer_t {
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name = "Buffer";
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desc = "";
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external queue_t multicast @ 0x100; // Not power-of-2 aligned
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};
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"""
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top = compile_rdl(rdl_source, top="buffer_t")
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with TemporaryDirectory() as tmpdir:
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exporter = BusDecoderExporter()
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# Should not raise an alignment error
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exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif)
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# Verify output was generated
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module_file = Path(tmpdir) / "buffer_t.sv"
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assert module_file.exists()
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content = module_file.read_text()
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# Verify the external component is in the generated code
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assert "multicast" in content
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def test_unaligned_external_component_array_supported(compile_rdl: Callable[..., AddrmapNode]) -> None:
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"""Test that external component arrays with non-power-of-2 strides are supported.
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This test verifies that external component arrays can have arbitrary strides,
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not just power-of-2 strides.
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"""
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rdl_source = """
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mem queue_t {
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name = "Queue";
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mementries = 256;
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memwidth = 32;
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};
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addrmap buffer_t {
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name = "Buffer";
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desc = "";
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external queue_t port[4] @ 0x0 += 0x600; // Stride of 0x600 (not power-of-2) to test unaligned support
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};
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"""
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top = compile_rdl(rdl_source, top="buffer_t")
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with TemporaryDirectory() as tmpdir:
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exporter = BusDecoderExporter()
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# Should not raise an alignment error
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exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif)
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# Verify output was generated
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module_file = Path(tmpdir) / "buffer_t.sv"
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assert module_file.exists()
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content = module_file.read_text()
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# Verify the external component array is in the generated code
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assert "port" in content
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def test_unaligned_external_nested_in_addrmap(compile_rdl: Callable[..., AddrmapNode]) -> None:
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"""Test that addrmaps containing external components can be at unaligned addresses.
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This verifies that not just external components themselves, but also
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non-external addrmaps/regfiles that contain external components can be
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at unaligned addresses.
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"""
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rdl_source = """
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mem queue_t {
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name = "Queue";
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mementries = 512;
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memwidth = 32;
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};
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addrmap inner_block {
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external queue_t ext_queue @ 0x0;
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};
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addrmap outer_block {
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inner_block inner @ 0x150; // Not power-of-2 aligned
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};
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"""
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top = compile_rdl(rdl_source, top="outer_block")
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with TemporaryDirectory() as tmpdir:
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exporter = BusDecoderExporter()
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# Should not raise an alignment error
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exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif)
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# Verify output was generated
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module_file = Path(tmpdir) / "outer_block.sv"
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assert module_file.exists()
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content = module_file.read_text()
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# Verify the nested components are in the generated code
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assert "inner" in content
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