33 lines
949 B
Systemverilog
33 lines
949 B
Systemverilog
{% sv_line_anchor %}
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apb3_intf #(
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.DATA_WIDTH({{exporter.cpuif.data_width}}),
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.ADDR_WIDTH({{exporter.cpuif.addr_width}})
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) s_apb();
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apb3_intf_driver #(
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.DATA_WIDTH({{exporter.cpuif.data_width}}),
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.ADDR_WIDTH({{exporter.cpuif.addr_width}})
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) cpuif (
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.clk(clk),
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.rst(rst),
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.m_apb(s_apb)
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);
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{% if type(cpuif).__name__.startswith("Flat") %}
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{% sv_line_anchor %}
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wire s_apb_psel;
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wire s_apb_penable;
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wire s_apb_pwrite;
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wire [{{exporter.cpuif.addr_width - 1}}:0] s_apb_paddr;
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wire [{{exporter.cpuif.data_width - 1}}:0] s_apb_pwdata;
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wire s_apb_pready;
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wire [{{exporter.cpuif.data_width - 1}}:0] s_apb_prdata;
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wire s_apb_pslverr;
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assign s_apb_psel = s_apb.PSEL;
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assign s_apb_penable = s_apb.PENABLE;
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assign s_apb_pwrite = s_apb.PWRITE;
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assign s_apb_paddr = s_apb.PADDR;
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assign s_apb_pwdata = s_apb.PWDATA;
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assign s_apb.PREADY = s_apb_pready;
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assign s_apb.PRDATA = s_apb_prdata;
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assign s_apb.PSLVERR = s_apb_pslverr;
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{% endif %}
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