129 lines
3.2 KiB
Systemverilog
129 lines
3.2 KiB
Systemverilog
interface apb4_intf_driver #(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 32
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)(
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input wire clk,
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input wire rst,
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apb4_intf.master m_apb
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);
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timeunit 1ps;
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timeprecision 1ps;
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logic PSEL;
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logic PENABLE;
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logic PWRITE;
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logic [2:0] PPROT;
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logic [ADDR_WIDTH-1:0] PADDR;
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logic [DATA_WIDTH-1:0] PWDATA;
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logic [DATA_WIDTH/8-1:0] PSTRB;
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logic [DATA_WIDTH-1:0] PRDATA;
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logic PREADY;
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logic PSLVERR;
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assign m_apb.PSEL = PSEL;
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assign m_apb.PENABLE = PENABLE;
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assign m_apb.PWRITE = PWRITE;
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assign m_apb.PPROT = PPROT;
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assign m_apb.PADDR = PADDR;
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assign m_apb.PWDATA = PWDATA;
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assign m_apb.PSTRB = PSTRB;
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assign PRDATA = m_apb.PRDATA;
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assign PREADY = m_apb.PREADY;
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assign PSLVERR = m_apb.PSLVERR;
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default clocking cb @(posedge clk);
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default input #1step output #1;
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output PSEL;
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output PENABLE;
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output PWRITE;
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output PPROT;
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output PADDR;
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output PWDATA;
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output PSTRB;
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input PRDATA;
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input PREADY;
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input PSLVERR;
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endclocking
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task automatic reset();
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cb.PSEL <= '0;
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cb.PENABLE <= '0;
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cb.PWRITE <= '0;
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cb.PPROT <= '0;
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cb.PADDR <= '0;
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cb.PWDATA <= '0;
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cb.PSTRB <= '0;
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endtask
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semaphore txn_mutex = new(1);
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task automatic write(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] data, logic [DATA_WIDTH/8-1:0] strb = '1);
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txn_mutex.get();
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##0;
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// Initiate transfer
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cb.PSEL <= '1;
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cb.PENABLE <= '0;
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cb.PWRITE <= '1;
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cb.PPROT <= '0;
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cb.PADDR <= addr;
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cb.PWDATA <= data;
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cb.PSTRB <= strb;
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@(cb);
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// active phase
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cb.PENABLE <= '1;
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@(cb);
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// Wait for response
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while(cb.PREADY !== 1'b1) @(cb);
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reset();
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txn_mutex.put();
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endtask
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task automatic read(logic [ADDR_WIDTH-1:0] addr, output logic [DATA_WIDTH-1:0] data);
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txn_mutex.get();
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##0;
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// Initiate transfer
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cb.PSEL <= '1;
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cb.PENABLE <= '0;
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cb.PWRITE <= '0;
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cb.PPROT <= '0;
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cb.PADDR <= addr;
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cb.PWDATA <= '0;
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cb.PSTRB <= '0;
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@(cb);
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// active phase
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cb.PENABLE <= '1;
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@(cb);
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// Wait for response
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while(cb.PREADY !== 1'b1) @(cb);
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assert(!$isunknown(cb.PRDATA)) else $error("Read from 0x%0x returned X's on PRDATA", addr);
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assert(!$isunknown(cb.PSLVERR)) else $error("Read from 0x%0x returned X's on PSLVERR", addr);
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data = cb.PRDATA;
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reset();
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txn_mutex.put();
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endtask
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task automatic assert_read(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] expected_data, logic [DATA_WIDTH-1:0] mask = '1);
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logic [DATA_WIDTH-1:0] data;
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read(addr, data);
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data &= mask;
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assert(data == expected_data) else $error("Read from 0x%x returned 0x%x. Expected 0x%x", addr, data, expected_data);
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endtask
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initial begin
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reset();
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end
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initial forever begin
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@cb;
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if(!rst) assert(!$isunknown(cb.PREADY)) else $error("Saw X on PREADY!");
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end
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endinterface
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