55 lines
1.7 KiB
Systemverilog
55 lines
1.7 KiB
Systemverilog
{% sv_line_anchor %}
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axi4lite_intf #(
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.DATA_WIDTH({{exporter.cpuif.data_width}}),
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.ADDR_WIDTH({{exporter.cpuif.addr_width}})
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) s_axil();
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axi4lite_intf_driver #(
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.DATA_WIDTH({{exporter.cpuif.data_width}}),
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.ADDR_WIDTH({{exporter.cpuif.addr_width}})
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) cpuif (
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.clk(clk),
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.rst(rst),
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.m_axil(s_axil)
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);
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{% if type(cpuif).__name__.startswith("Flat") %}
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{% sv_line_anchor %}
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wire s_axil_awready;
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wire s_axil_awvalid;
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wire [{{exporter.cpuif.addr_width - 1}}:0] s_axil_awaddr;
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wire [2:0] s_axil_awprot;
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wire s_axil_wready;
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wire s_axil_wvalid;
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wire [{{exporter.cpuif.data_width - 1}}:0] s_axil_wdata;
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wire [{{exporter.cpuif.data_width_bytes - 1}}:0] s_axil_wstrb;
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wire s_axil_bready;
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wire s_axil_bvalid;
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wire [1:0] s_axil_bresp;
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wire s_axil_arready;
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wire s_axil_arvalid;
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wire [{{exporter.cpuif.addr_width - 1}}:0] s_axil_araddr;
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wire [2:0] s_axil_arprot;
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wire s_axil_rready;
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wire s_axil_rvalid;
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wire [{{exporter.cpuif.data_width - 1}}:0] s_axil_rdata;
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wire [1:0] s_axil_rresp;
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assign s_axil.AWREADY = s_axil_awready;
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assign s_axil_awvalid = s_axil.AWVALID;
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assign s_axil_awaddr = s_axil.AWADDR;
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assign s_axil_awprot = s_axil.AWPROT;
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assign s_axil.WREADY = s_axil_wready;
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assign s_axil_wvalid = s_axil.WVALID;
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assign s_axil_wdata = s_axil.WDATA;
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assign s_axil_wstrb = s_axil.WSTRB;
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assign s_axil_bready = s_axil.BREADY;
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assign s_axil.BVALID = s_axil_bvalid;
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assign s_axil.BRESP = s_axil_bresp;
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assign s_axil.ARREADY = s_axil_arready;
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assign s_axil_arvalid = s_axil.ARVALID;
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assign s_axil_araddr = s_axil.ARADDR;
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assign s_axil_arprot = s_axil.ARPROT;
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assign s_axil_rready = s_axil.RREADY;
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assign s_axil.RVALID = s_axil_rvalid;
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assign s_axil.RDATA = s_axil_rdata;
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assign s_axil.RRESP = s_axil_rresp;
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{% endif %}
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