124 lines
3.8 KiB
Systemverilog
124 lines
3.8 KiB
Systemverilog
interface passthrough_driver #(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 32
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)(
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input wire clk,
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input wire rst,
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output logic m_cpuif_req,
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output logic m_cpuif_req_is_wr,
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output logic [ADDR_WIDTH-1:0] m_cpuif_addr,
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output logic [DATA_WIDTH-1:0] m_cpuif_wr_data,
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output logic [DATA_WIDTH-1:0] m_cpuif_wr_biten,
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input wire m_cpuif_req_stall_wr,
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input wire m_cpuif_req_stall_rd,
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input wire m_cpuif_rd_ack,
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input wire m_cpuif_rd_err,
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input wire [DATA_WIDTH-1:0] m_cpuif_rd_data,
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input wire m_cpuif_wr_ack,
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input wire m_cpuif_wr_err
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);
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timeunit 1ps;
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timeprecision 1ps;
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default clocking cb @(posedge clk);
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default input #1step output #1;
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output m_cpuif_req;
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output m_cpuif_req_is_wr;
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output m_cpuif_addr;
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output m_cpuif_wr_data;
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output m_cpuif_wr_biten;
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input m_cpuif_req_stall_wr;
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input m_cpuif_req_stall_rd;
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input m_cpuif_rd_ack;
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input m_cpuif_rd_err;
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input m_cpuif_rd_data;
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input m_cpuif_wr_ack;
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input m_cpuif_wr_err;
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endclocking
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task automatic reset();
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cb.m_cpuif_req <= '0;
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cb.m_cpuif_req_is_wr <= '0;
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cb.m_cpuif_addr <= '0;
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cb.m_cpuif_wr_data <= '0;
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cb.m_cpuif_wr_biten <= '0;
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endtask
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semaphore txn_req_mutex = new(1);
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semaphore txn_resp_mutex = new(1);
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task automatic write(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] data, logic [DATA_WIDTH-1:0] biten = '1);
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fork
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begin
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// Initiate transfer
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txn_req_mutex.get();
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##0;
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cb.m_cpuif_req <= '1;
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cb.m_cpuif_req_is_wr <= '1;
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cb.m_cpuif_addr <= addr;
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cb.m_cpuif_wr_data <= data;
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cb.m_cpuif_wr_biten <= biten;
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@(cb);
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while(cb.m_cpuif_req_stall_wr !== 1'b0) @(cb);
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reset();
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txn_req_mutex.put();
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end
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begin
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// Wait for response
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txn_resp_mutex.get();
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@cb;
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while(cb.m_cpuif_wr_ack !== 1'b1) @(cb);
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txn_resp_mutex.put();
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end
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join
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endtask
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task automatic read(logic [ADDR_WIDTH-1:0] addr, output logic [DATA_WIDTH-1:0] data);
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fork
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begin
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// Initiate transfer
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txn_req_mutex.get();
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##0;
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cb.m_cpuif_req <= '1;
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cb.m_cpuif_req_is_wr <= '0;
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cb.m_cpuif_addr <= addr;
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@(cb);
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while(cb.m_cpuif_req_stall_rd !== 1'b0) @(cb);
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reset();
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txn_req_mutex.put();
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end
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begin
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// Wait for response
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txn_resp_mutex.get();
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@cb;
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while(cb.m_cpuif_rd_ack !== 1'b1) @(cb);
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assert(!$isunknown(cb.m_cpuif_rd_data)) else $error("Read from 0x%0x returned X's on m_cpuif_rd_data", addr);
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data = cb.m_cpuif_rd_data;
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txn_resp_mutex.put();
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end
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join
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endtask
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task automatic assert_read(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] expected_data, logic [DATA_WIDTH-1:0] mask = '1);
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logic [DATA_WIDTH-1:0] data;
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read(addr, data);
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data &= mask;
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assert(data == expected_data) else $error("Read from 0x%x returned 0x%x. Expected 0x%x", addr, data, expected_data);
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endtask
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initial begin
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reset();
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end
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initial forever begin
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@cb;
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if(!rst) assert(!$isunknown(cb.m_cpuif_rd_ack)) else $error("Saw X on m_cpuif_rd_ack!");
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if(!rst) assert(!$isunknown(cb.m_cpuif_wr_ack)) else $error("Saw X on m_cpuif_wr_ack!");
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end
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endinterface
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