33 lines
1.0 KiB
Systemverilog
33 lines
1.0 KiB
Systemverilog
{% sv_line_anchor %}
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wire s_cpuif_req;
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wire s_cpuif_req_is_wr;
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wire [{{exporter.cpuif.addr_width-1}}:0] s_cpuif_addr;
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wire [{{exporter.cpuif.data_width-1}}:0] s_cpuif_wr_data;
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wire [{{exporter.cpuif.data_width-1}}:0] s_cpuif_wr_biten;
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wire s_cpuif_req_stall_wr;
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wire s_cpuif_req_stall_rd;
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wire s_cpuif_rd_ack;
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wire s_cpuif_rd_err;
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wire [{{exporter.cpuif.data_width-1}}:0] s_cpuif_rd_data;
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wire s_cpuif_wr_ack;
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wire s_cpuif_wr_err;
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passthrough_driver #(
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.DATA_WIDTH({{exporter.cpuif.data_width}}),
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.ADDR_WIDTH({{exporter.cpuif.addr_width}})
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) cpuif (
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.clk(clk),
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.rst(rst),
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.m_cpuif_req(s_cpuif_req),
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.m_cpuif_req_is_wr(s_cpuif_req_is_wr),
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.m_cpuif_addr(s_cpuif_addr),
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.m_cpuif_wr_data(s_cpuif_wr_data),
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.m_cpuif_wr_biten(s_cpuif_wr_biten),
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.m_cpuif_req_stall_wr(s_cpuif_req_stall_wr),
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.m_cpuif_req_stall_rd(s_cpuif_req_stall_rd),
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.m_cpuif_rd_ack(s_cpuif_rd_ack),
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.m_cpuif_rd_err(s_cpuif_rd_err),
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.m_cpuif_rd_data(s_cpuif_rd_data),
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.m_cpuif_wr_ack(s_cpuif_wr_ack),
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.m_cpuif_wr_err(s_cpuif_wr_err)
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);
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