11 lines
347 B
Python
11 lines
347 B
Python
from jinja2_simple_tags import StandaloneTag
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class SVLineAnchor(StandaloneTag):
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"""
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Define a custom Jinja tag that emits a SystemVerilog `line directive so that
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assertion messages can get properly back-annotated
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"""
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tags = {"sv_line_anchor"}
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def render(self):
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return f'`line {self.lineno + 1} "{self.template}" 0'
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