198 lines
5.0 KiB
Systemverilog
198 lines
5.0 KiB
Systemverilog
{% extends "lib/tb_base.sv" %}
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{% block seq %}
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{% sv_line_anchor %}
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logic [15:0] counter;
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logic [7:0] rd_data_l;
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logic [7:0] rd_data_h;
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logic [15:0] latched_data;
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int event_count;
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bit fired;
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latched_data = 'x;
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##1;
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cb.rst <= '0;
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##1;
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// Verify that hwif gets sampled at the same cycle as swacc strobe
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counter = 'h10;
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cb.hwif_in.r1.f.next <= counter;
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@cb;
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event_count = 0;
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fork
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begin
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##0;
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forever begin
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counter++;
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cb.hwif_in.r1.f.next <= counter;
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@cb;
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if(cb.hwif_out.r1.f.swacc) begin
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latched_data = counter;
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event_count++;
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end
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end
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end
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begin
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cpuif.read('h0, rd_data_l);
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cpuif.read('h1, rd_data_h);
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repeat(3) @cb;
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end
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join_any
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disable fork;
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assert({rd_data_h, rd_data_l} == latched_data) else $error("Read returned 0x%0x but swacc strobed during 0x%0x", {rd_data_h, rd_data_l}, latched_data);
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assert(event_count == 1) else $error("Observed excess swacc events: %0d", event_count);
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// Verify that hwif changes 1 cycle after swmod
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fired = 0;
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fork
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begin
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##0;
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forever begin
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assert(cb.hwif_out.r2.f.value == 'h4020);
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if(cb.hwif_out.r2.f.swmod) break;
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@cb;
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end
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fired = 1;
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@cb;
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forever begin
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assert(cb.hwif_out.r2.f.value == 'h4221);
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assert(cb.hwif_out.r2.f.swmod == 0);
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@cb;
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end
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end
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begin
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cpuif.write('h2, 'h21);
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cpuif.write('h3, 'h42);
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repeat(3) @cb;
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end
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join_any
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disable fork;
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assert(fired);
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// Verify that hwif changes 1 cycle after swmod
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fired = 0;
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fork
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begin
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##0;
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forever begin
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assert(cb.hwif_out.r3.f.value == 'h1030);
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if(cb.hwif_out.r3.f.swmod) break;
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@cb;
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end
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fired = 1;
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@cb;
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forever begin
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assert(cb.hwif_out.r3.f.value == 0);
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assert(cb.hwif_out.r3.f.swmod == 0);
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@cb;
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end
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end
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begin
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cpuif.assert_read('h4, 'h30);
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cpuif.assert_read('h5, 'h10);
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repeat(3) @cb;
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end
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join_any
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disable fork;
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assert(fired);
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// Verify swacc and swmod assert when written
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fired = 0;
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fork
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begin
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##0;
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forever begin
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assert(cb.hwif_out.r4.f.value == 'h1234);
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if(cb.hwif_out.r4.f.swmod || cb.hwif_out.r4.f.swacc) begin
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assert(cb.hwif_out.r4.f.swmod == 1);
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assert(cb.hwif_out.r4.f.swacc == 1);
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break;
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end
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@cb;
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end
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fired = 1;
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@cb;
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forever begin
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assert(cb.hwif_out.r4.f.value == 'h4567);
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assert(cb.hwif_out.r4.f.swmod == 0);
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assert(cb.hwif_out.r4.f.swacc == 0);
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@cb;
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end
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end
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begin
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cpuif.write('h6, 'h67);
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cpuif.write('h7, 'h45);
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repeat(3) @cb;
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end
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join_any
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disable fork;
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assert(fired);
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// Verify swacc and swmod assert when written
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fired = 0;
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fork
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begin
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##0;
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forever begin
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assert(cb.hwif_out.r5.f.value == 'hABCD);
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if(cb.hwif_out.r5.f.swmod || cb.hwif_out.r5.f.swacc) begin
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assert(cb.hwif_out.r5.f.swmod == 1);
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assert(cb.hwif_out.r5.f.swacc == 1);
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break;
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end
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@cb;
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end
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fired = 1;
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@cb;
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forever begin
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assert(cb.hwif_out.r5.f.value == 'hEF12);
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assert(cb.hwif_out.r5.f.swmod == 0);
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assert(cb.hwif_out.r5.f.swacc == 0);
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@cb;
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end
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end
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begin
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cpuif.write('h8, 'h12);
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cpuif.write('h9, 'hEF);
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repeat(3) @cb;
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end
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join_any
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disable fork;
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assert(fired);
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// Verify that hwif changes 1 cycle after swmod
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fired = 0;
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fork
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begin
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##0;
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forever begin
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assert(cb.hwif_out.r6.f.value == 'h1030);
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if(cb.hwif_out.r6.f.swmod) break;
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@cb;
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end
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fired = 1;
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@cb;
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forever begin
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assert(cb.hwif_out.r6.f.value == 0);
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assert(cb.hwif_out.r6.f.swmod == 0);
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@cb;
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end
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end
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begin
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cpuif.assert_read('ha, 'h30);
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cpuif.assert_read('hb, 'h10);
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repeat(3) @cb;
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end
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join_any
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disable fork;
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assert(fired);
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{% endblock %}
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