69 lines
1.6 KiB
Systemverilog
69 lines
1.6 KiB
Systemverilog
{% extends "lib/tb_base.sv" %}
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{% block seq %}
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{% sv_line_anchor %}
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logic [7:0] counter;
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logic [7:0] rd_data;
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logic [7:0] latched_data;
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int event_count;
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latched_data = 'x;
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##1;
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cb.rst <= '0;
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##1;
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// Verify that hwif gets sampled at the same cycle as rd_swacc strobe
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counter = 'h10;
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cb.hwif_in.r1.f.next <= counter;
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@cb;
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event_count = 0;
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fork
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begin
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##0;
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forever begin
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counter++;
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cb.hwif_in.r1.f.next <= counter;
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@cb;
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if(cb.hwif_out.r1.f.rd_swacc) begin
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latched_data = counter;
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event_count++;
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end
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end
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end
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begin
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cpuif.read('h0, rd_data);
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@cb;
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end
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join_any
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disable fork;
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assert(rd_data == latched_data) else $error("Read returned 0x%0x but rd_swacc strobed during 0x%0x", rd_data, latched_data);
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assert(event_count == 1) else $error("Observed excess rd_swacc events: %0d", event_count);
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// Verify that hwif changes 1 cycle after wr_swacc
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fork
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begin
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##0;
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forever begin
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assert(cb.hwif_out.r2.f.value == 20);
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if(cb.hwif_out.r2.f.wr_swacc) break;
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@cb;
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end
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@cb;
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forever begin
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assert(cb.hwif_out.r2.f.value == 21);
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assert(cb.hwif_out.r2.f.wr_swacc == 0);
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@cb;
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end
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end
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begin
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cpuif.write('h1, 21);
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@cb;
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end
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join_any
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disable fork;
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{% endblock %}
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