27 lines
548 B
Systemverilog
27 lines
548 B
Systemverilog
{% extends "lib/tb_base.sv" %}
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{% block seq %}
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{% sv_line_anchor %}
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##1;
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cb.rst <= '0;
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##1;
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// Always write both fields from hardware
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cb.hwif_in.r1.f_sw.next <= '0;
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cb.hwif_in.r1.f_sw.we <= '1;
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cb.hwif_in.r1.f_hw.next <= '0;
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cb.hwif_in.r1.f_hw.we <= '1;
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@cb;
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@cb;
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cpuif.assert_read('h0, 'b00);
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cpuif.assert_read('h4, 'h00);
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cpuif.write('h0, 'b11);
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cpuif.write('h0, 'b11);
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cpuif.write('h0, 'b11);
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cpuif.assert_read('h0, 'h00);
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cpuif.assert_read('h4, 'h03);
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{% endblock %}
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