147 lines
3.8 KiB
Systemverilog
147 lines
3.8 KiB
Systemverilog
{% extends "lib/tb_base.sv" %}
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{% block seq %}
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{% sv_line_anchor %}
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cb.hwif_in.incr_en <= '1;
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cb.hwif_in.trigger_sig_n <= '1;
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##1;
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cb.rst <= '0;
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##1;
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//--------------------------------------------------------------------------
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// Wide registers
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//--------------------------------------------------------------------------
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// reg1
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// expect to read all counter values atomically
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begin
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logic [7:0] subword;
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logic [31:0] rdata;
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logic [2:0] fdata;
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cpuif.read('h0, subword);
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fdata = subword[2:0];
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rdata = {10{fdata}};
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assert(subword == rdata[7:0]);
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cpuif.assert_read('h1, rdata[15:8]);
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cpuif.assert_read('h2, rdata[23:16]);
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cpuif.assert_read('h3, rdata[31:24]);
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end
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// reg1_msb0
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// expect to read all counter values atomically
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begin
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logic [7:0] subword;
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logic [31:0] rdata;
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logic [2:0] fdata;
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cpuif.read('h4, subword);
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fdata = subword[3:1];
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rdata = {10{fdata}} << 1;
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assert(subword == rdata[7:0]);
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cpuif.assert_read('h5, rdata[15:8]);
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cpuif.assert_read('h6, rdata[23:16]);
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cpuif.assert_read('h7, rdata[31:24]);
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end
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cb.hwif_in.incr_en <= '0;
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@cb;
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// check that msb0 ordering is correct
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begin
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logic [7:0] subword;
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logic [31:0] rdata;
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logic [2:0] fdata;
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cpuif.read('h0, subword);
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fdata = subword[2:0];
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rdata = {10{fdata}};
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assert(subword == rdata[7:0]);
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cpuif.assert_read('h1, rdata[15:8]);
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cpuif.assert_read('h2, rdata[23:16]);
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cpuif.assert_read('h3, rdata[31:24]);
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fdata = {<<{fdata}};
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rdata = {10{fdata}} << 1;
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cpuif.assert_read('h4, rdata[7:0]);
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cpuif.assert_read('h5, rdata[15:8]);
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cpuif.assert_read('h6, rdata[23:16]);
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cpuif.assert_read('h7, rdata[31:24]);
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end
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cb.hwif_in.incr_en <= '1;
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// reg2
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// read-clear
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repeat(2) begin
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logic [7:0] subword;
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logic [4:0] fdata;
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logic [31:0] rdata;
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cpuif.read('h8, subword);
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rdata[7:0] = subword;
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cpuif.read('h9, subword);
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rdata[15:8] = subword;
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cpuif.read('hA, subword);
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rdata[23:16] = subword;
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cpuif.read('hB, subword);
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rdata[31:24] = subword;
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fdata = rdata[4:0];
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assert(rdata[14:10] == fdata);
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assert(rdata[26:22] == fdata);
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assert(rdata[31:27] == fdata);
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end
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//--------------------------------------------------------------------------
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// Alternate Triggers
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//--------------------------------------------------------------------------
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// Trigger via another register
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// g1
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begin
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logic [7:0] rdata;
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cpuif.read('hC, rdata);
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cpuif.assert_read('hD, rdata);
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end
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// g2
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begin
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logic [7:0] rdata1;
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logic [7:0] rdata2;
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cpuif.read('h10, rdata1);
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cpuif.read('h11, rdata2);
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cpuif.assert_read('h12, rdata1);
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cpuif.assert_read('h13, rdata2);
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end
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// triger from signal
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// g3
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cb.hwif_in.g3_r1.f1.next <= 'hAB;
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cb.hwif_in.g3_r2.f1.next <= 'hCD;
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cb.hwif_in.trigger_sig <= '1;
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cb.hwif_in.trigger_sig_n <= '0;
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@cb;
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cb.hwif_in.g3_r1.f1.next <= 'h00;
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cb.hwif_in.g3_r2.f1.next <= 'h00;
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cb.hwif_in.trigger_sig <= '0;
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cb.hwif_in.trigger_sig_n <= '1;
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@cb;
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cpuif.assert_read('h14, 'hAB);
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cpuif.assert_read('h15, 'hCD);
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// trigger from field/propref
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// g4
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begin
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logic [7:0] rdata;
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cpuif.write('h16, 'h1);
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repeat(5) @cb;
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cpuif.read('h17, rdata);
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repeat(5) @cb;
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cpuif.assert_read('h18, rdata - 1); // swmod happens one cycle earlier, so count is -1
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end
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{% endblock %}
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