112 lines
2.1 KiB
Plaintext
112 lines
2.1 KiB
Plaintext
addrmap top {
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reg {
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regwidth = 64;
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accesswidth = 16;
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default sw=rw;
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default hw=r;
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field {} f1[7:0] = 0;
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field {} f2[14:12] = 0;
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field {} f3[36:36] = 0;
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field {} f4[47:40] = 0;
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} rw_reg1;
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reg {
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regwidth = 64;
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accesswidth = 16;
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default sw=rw;
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default hw=r;
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field {} f1[19:16] = 0;
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field {} f2[63:48] = 0;
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} rw_reg2;
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reg {
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regwidth = 64;
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accesswidth = 16;
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default sw=rw;
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default hw=r;
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field {} f1[0:7] = 0;
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field {} f2[12:14] = 0;
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field {} f3[36:36] = 0;
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field {} f4[40:47] = 0;
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} rw_reg1_lsb0;
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reg {
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regwidth = 64;
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accesswidth = 16;
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default sw=rw;
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default hw=r;
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field {} f1[16:19] = 0;
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field {} f2[48:63] = 0;
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} rw_reg2_lsb0;
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reg {
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regwidth = 32;
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accesswidth = 16;
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default sw=r;
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default hw=w;
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field {
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sw=w; hw=r;
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} f0[3:3] = 0;
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field {} f1[19:12];
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field {} f2[30:20];
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} r_reg;
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reg {
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regwidth = 32;
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accesswidth = 16;
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default sw=r;
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default hw=w;
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field {} f1[12:19];
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field {} f2[20:30];
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} r_reg_lsb0;
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reg {
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regwidth = 64;
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accesswidth = 16;
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default sw=r;
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default hw=w;
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field {} f1[31:12];
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field {} f2[49:48];
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} r_reg2;
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reg {
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regwidth=16;
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field {
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sw=r; hw=na;
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counter;
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} f1_cnt[7:0] = 0;
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field {
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sw=r; hw=na;
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counter;
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} f2_cnt[15:8] = 0;
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} counter_reg;
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counter_reg.f1_cnt->incr = r_reg2.f1->swacc;
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counter_reg.f2_cnt->incr = r_reg2.f2->swacc;
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reg {
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regwidth = 32;
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accesswidth = 16;
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default sw=r;
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default hw=r;
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field {} f1[31:0] = 0x1234_5678;
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} r_reg3;
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reg {
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regwidth = 32;
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accesswidth = 16;
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default sw=r;
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default hw=r;
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field {} f1[0:31] = 0x1234_5678;
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} r_reg4;
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};
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